Programming Model

24.5.4 I2C Status Register (I2SR)

This I2SR contains bits that indicate transaction direction and status.

Field

Reset

R/W

Address

7

6

5

4

3

2

1

0

ICF

IAAS

IBB

IAL

 

SRW

IIF

RXAK

 

 

 

 

 

 

 

 

 

 

 

 

1000_0001

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

R/W

 

R

R/W

R

 

 

 

 

 

 

 

 

 

IPSBAR + 0x30C

Figure 24-8. I2CR Status Register (I2SR)

Table 24-5describes I2SR fields.

 

 

 

Table 24-5. I2SR Field Descriptions

 

 

 

 

Bits

Name

 

Description

 

 

 

7

ICF

Data transferring bit. While one byte of data is transferred, ICF is cleared.

 

 

0

Transfer in progress

 

 

1

Transfer complete. Set by the falling edge of the ninth clock of a byte transfer.

 

 

 

6

IAAS

I2C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check SRW and

 

 

set its TX/RX mode accordingly. Writing to I2CR clears this bit.

 

 

0

Not addressed.

 

 

1

Addressed as a slave. Set when its own address (IADR) matches the calling address.

 

 

 

5

IBB

I2C bus busy bit. Indicates the status of the bus.

 

 

0

Bus is idle. If a STOP signal is detected, IBB is cleared.

 

 

1

Bus is busy. When START is detected, IBB is set.

 

 

 

4

IAL

Arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by software by writing

 

 

zero to it.)

 

 

SDA sampled low when the master drives high during an address or data-transmit cycle.

 

 

SDA sampled low when the master drives high during the acknowledge bit of a data-receive cycle.

 

 

A start cycle is attempted when the bus is busy.

 

 

A repeated start cycle is requested in slave mode.

 

 

A stop condition is detected when the master did not request it.

 

 

 

3

Reserved, should be cleared.

 

 

 

2

SRW

Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of the calling address

 

 

sent from the master. SRW is valid only when a complete transfer has occurred, no other transfers have been

 

 

initiated, and the I2C module is a slave and has an address match.

 

 

0

Slave receive, master writing to slave.

 

 

1

Slave transmit, master reading from slave.

 

 

 

 

MOTOROLA

Chapter 24. I2C Interface

24-9

Page 519
Image 519
Motorola MCF5281, MCF5282 user manual 24.5.4 I2C Status Register I2SR, 5describes I2SR fields, I2SR Field Descriptions