Motorola MCF5281, MCF5282 Qadc Electrical Characteristics, Qadc Absolute Maximum Ratings

QADC Electrical Characteristics

8Assuming a reference is available at power up, lock time is measured from the time VDD and VDDPLL are valid to RSTO negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time must be added to the PLL lock time to determine the total start-up time.

9PLL is operating in 1:1 PLL mode.

10Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval

11Based on slow system clock of 40 MHz measured at fsys max.

33.5 QADC Electrical Characteristics

Table 33-5. QADC Absolute Maximum Ratings

				Parameter		Symbol			Min	Max	Unit
Analog Supply, with reference to VSSA						VDDA			–0.3	6.0	V
Internal Digital Supply 1, with reference to VSS						VDD			–0.3	4.0	V
Reference Supply, with reference to VRL						VRH			–0.3	6.0	V
VSS Differential Voltage					VSS – VSSA				–0.1	0.1	V
VDD Differential Voltage 2					VDD – VDDA				–6.0	4.0	V
VREF Differential Voltage					VRH – VRL				–0.3	6.0	V
V	RH	to V	DDA	Differential Voltage 3	V	RH	– V	DDA	–6.0	6.0	V
VRL to VSSA Differential Voltage					VRL – VSSA				–0.3	0.3	V
VDDH to VDDA Differential Voltage					VDDH – VDDA				–1.0	1.0	V
Maximum Input Current 4, 5, 6							IMA		–25	25	mA

1For internal digital supply of VDD = 3.3V typical.

2Refers to allowed random sequencing of power supplies.

3Refers to allowed random sequencing of power supplies.

4Transitions within the limit do not affect device reliability or cause permanent damage. Exceeding limit may cause permanent conversion error on stressed channels and on unstressed channels.

5Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.3V and VNEGCLAMP = –0.3 V, then use the larger of the calculated values.

6Condition applies to one pin at a time.

Table 33-6. QADC Electrical Specifications (Operating) 1

(VDDH and VDDA = 5.0 Vdc ± 0.5V, VDD = 2.7-3.6V, VSS and VSSA = 0 Vdc, FQCLK = 2.0 MHz, TA within operating temperature range)

Parameter	Symbol			Min		Max	Unit
Analog Supply	VDDA			3.3		5.5	V
VSS Differential Voltage	VSS – VSSA			-100		100	mV
Reference Voltage Low 2	VRL			VSSA		VSSA + 0.1	V
Reference Voltage High 2	V	RH	V	DDA	– 0.1	V	V
						DDA
VREF Differential Voltage	VRH – VRL			3.3		5.5	V

MOTOROLA Chapter 33. Electrical Characteristics 33-7