Motorola MCF5282 Phase Lock Loop Electrical Specifications, PLL Electrical Specifications

Phase Lock Loop Electrical Specifications

33.4 Phase Lock Loop Electrical Specifications

Table 33-4. PLL Electrical Specifications

(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V)

Characteristic		Symbol	Min	Max	Unit
PLL Reference Frequency Range					MHz
Crystal reference		fref_crystal	2	10.0
External reference		fref_ext	2	10.0
1:1 Mode		fref_1:1	33.33	80
System Frequency 1		fsys	0	80	MHz
External Clock Mode
On-Chip PLL Frequency			fref / 32	80
Loss of Reference Frequency 2, 4		fLOR	100	1000	kHz
Self Clocked Mode Frequency 3, 4		fSCM	1	5	MHz
Crystal Start-up Time 4, 5		t	—	10	ms
		cst
EXTAL Input High Voltage		VIHEXT			V
Crystal Mode			VDD- 1.0	VDD
All other modes (1:1, Bypass, External)			2.0	VDD
EXTAL Input Low Voltage		VILEXT			V
Crystal Mode			VSS	1.0
All other modes (1:1, Bypass, External)			VSS	0.8
XTAL Output High Voltage		VOL			V
IOH = 1.0 mA			VDD- 1.0	—
XTAL Output Low Voltage		VOL			V
IOL = 1.0 mA			—	0.5
XTAL Load Capacitance6			—	—	pF
PLL Lock Time4,7		tlpll	—	500	∝s
Power-up To Lock Time 4, 5,8		tlplk	—	10.5	ms
With Crystal Reference
Without Crystal Reference			—	500	∝s
1:1 Clock Skew (between CLKOUT and EXTAL) 9		t	-2	2	ns
		skew
Duty Cycle of reference 4		t	40	60	% f	sys
		dc
Frequency un-LOCK Range		fUL	- 1.5	1.5	% fsys
Frequency LOCK Range		fLCK	- 0.75	0.75	% % fsys
CLKOUT Period Jitter 4, 5, 7, 10,11 , Measured at f	Max	C
SYS		jitter
Peak-to-peak Jitter (Clock edge to clock edge)			—	10	% fsys
Long Term Jitter (Averaged over 2 ms interval)			—	.01

1All internal registers retain data at 0 Hz.

2“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.

3Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR with default MFD/RFD settings.

4This parameter is characterized before qualification rather than 100% tested.

5Proper PC board layout procedures must be followed to achieve specifications.

6Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics.

7This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR).

33-6 MCF5282 User’s Manual MOTOROLA