Motorola MCF5281, MCF5282 user manual Processor Pipelines, Iag, Fifo, Dsoc, Agex

Chapter 2

ColdFire Core

This section describes the organization of the Version 2 (V2) ColdFire® processor core and an overview of the program-visible registers. For detailed information on instructions, see the ColdFire Family Programmer’s Reference Manual.

2.1Processor Pipelines

Figure 2-1is a block diagram showing the processor pipelines of a V2 ColdFire core.

	IAG	Instruction
		Address
		Generation
	IC	Instruction
		Fetch Cycle
Instruction
Fetch
Pipeline
	IB	FIFO
		Instruction Buffer
Operand	DSOC	Decode & Select,
		Operand Fetch
Execution
Pipeline		Address
	AGEX
		Generation,
		Execute

Address [31:0]

read_data[31:0]

write_data[31:0]

Figure 2-1. ColdFire Processor Core Pipelines

MOTOROLA Chapter 2. ColdFire Core 2-1