Motorola MCF5282, MCF5281 user manual PLL Operation, Phase and Frequency Detector PFD

Functional Description

3.Write the MFD value from step 1 to the SYNCR.

4.Monitor the LOCK flag in SYNSR. When the PLL achieves lock, write the RFD value from step 1 to the RFD field of the SYNCR. This changes the system clocks frequency to the required frequency.

NOTE

Keep the maximum system clock frequency below the limit given in the Electrical Characteristics.

9.7.4PLL Operation

In PLL mode, the PLL synthesizes the system clocks. The PLL can multiply the reference clock frequency by 2x to 9x, provided that the system clock frequency remains within the range listed in electrical specifications. For example, if the reference frequency is 2 MHz, the PLL can synthesize frequencies of 4 MHz to 18 MHz. In addition, the RFD can reduce the system frequency by dividing the output of the PLL. The RFD is not in the feedback loop of the PLL, so changing the RFD divisor does not affect PLL operation.

Figure 9-5shows the external support circuitry for the crystal oscillator with example component values. Actual component values depend on crystal specifications.

The following subsections describe each major block of the PLL. Refer to Figure to see how these functional sub-blocks interact.

				8-MHz CRYSTAL CONFIGURATIO
				C1 = C2 = 16 pF
C1			C2	RF = 1 MΩ
				RS = 470 Ω
VSS	EXTAL	XTAL	VSSSYN
ON-CHIP		RS
		RF

Figure 9-5. Crystal Oscillator Example

9.7.4.1Phase and Frequency Detector (PFD)

The PFD is a dual-latch phase-frequency detector. It compares both the phase and frequency of the reference and feedback clocks. The reference clock comes from either the crystal oscillator or an external clock source.

9-12 MCF5282 User’s Manual MOTOROLA