Motorola MCF5282, MCF5281 user manual Self-Refresh Operation, Auto-Refresh Operation

SDRAM Controller Operation

request flag. This refresh cycle includes a delay from any precharge to the auto-refresh command, the auto-refresh command, and then a delay until any ACTV command is allowed. Any SDRAM access initiated during the auto-refresh cycle is delayed until the cycle is completed.

Figure 15-8shows the auto-refresh timing. In this case, there is an SDRAM access when the refresh request becomes active. The request is delayed by the precharge to ACTV delay programmed into the active SDRAM bank by the CAS bits. The REF command is then generated and the delay required by DCR[RTIM] is inserted before the next ACTV command is generated. In this example, the next bus cycle is initiated, but does not generate an SDRAM access until TRC is finished. Because both chip selects are active during the REF command, it is passed to both blocks of external SDRAM.

CLKOUT

A[31:0]

SRAS

tRCD = 2

SCAS

DRAMW

SDRAM_CS[0] or [1]

PALL

tRC = 6

REF ACTV

Figure 15-8. Auto-Refresh Operation

15.2.3.6Self-Refresh Operation

Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at the same time to perform an internal refresh operation and to maintain the integrity of the data stored in the SDRAM. The DRAM controller supports self-refresh with DCR[IS]. When IS is set, the SELF command is sent to the SDRAM. When IS is cleared, the SELFX command is sent to the DRAM controller. Figure 15-9shows the self-refresh operation.

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