Motorola MCF5281, MCF5282 user manual Chapter Interrupt Controller Modules

Chapter 10

Interrupt Controller Modules

This section details the functionality for the MCF5282 interrupt controllers (INTC0, INTC1). The general features of each of the interrupt controller include:

•63 interrupt sources, organized as:

—56 fully-programmable interrupt sources

—7 fixed-level interrupt sources

•Each of the 63 sources has a unique interrupt control register (ICRnx) to define the software-assigned levels and priorities within the level

•Unique vector number for each interrupt source

•Ability to mask any individual interrupt source, plus global mask-all capability

•Supports both hardware and software interrupt acknowledge cycles

•“Wake-up” signal from low-power stop modes

The 56 fully-programmable and seven fixed-level interrupt sources for each of the two interrupt controllers on the MCF5282 handle the complete set of interrupt sources from all of the modules on the device. This section describes how the interrupt sources are mapped to the interrupt controller logic and how interrupts are serviced.

10.1 68K/ColdFire Interrupt Architecture Overview

Before continuing with the specifics of the MCF5282 interrupt controllers, a brief review of the interrupt architecture of the 68K/ColdFire family is appropriate.

The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a 3-bit encoded interrupt priority level sent from the interrupt controller to the core, providing 7 levels of interrupt requests. Level 7 represents the highest priority interrupt level, while level 1 is the lowest priority. The processor samples for active interrupt requests once per instruction by comparing the encoded priority level against a 3-bit interrupt mask value (I) contained in bits 10:8 of the machine’s status register (SR). If the priority level is greater than the SR[I] field at the sample point, the processor suspends normal instruction execution and initiates interrupt exception processing. Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and may be masked depending on the value of the SR[I] field. For

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