Motorola MCF5281, MCF5282 user manual Uart Module Signal Definitions, Irq, Ucts

UART Module Signal Definitions

23.4 UART Module Signal Definitions

Figure 23-16shows both the external and internal signal groups.

System Clock

or

External Clock (DTIN)

Clock Source

Generator

Output Port

URTS

Interface to CPU

To Interrupt

Controller

or DMA

UART Module

Internal Bus

Control
	Internal
	Control
Address Bus	Logic
	Data
	IRQ

Input Port

Four-Character Receive Buffer

Two-Character Transmit Buffer

UCTS

URXD

UTXD

External

Interface

Signals

Figure 23-16. UART Block Diagram Showing External and Internal Interface Signals

An internal interrupt request signal (IRQ) is provided to notify the interrupt controller of an interrupt condition. The output is the logical NOR of unmasked UISRn bits. The interrupt level of a UART module is programmed in the interrupt controller.

The interrupt level and priority is programmed in the interrupt controller—ICR13 for UART0, ICR14 for UART1, and ICR15 for UART2. See Section 10.3.6, “Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)).”

Note that the UARTs can also be configured to automatically transfer data by using the DMA rather than interrupting the core. When the FIFO has data on the receive path, a DMA request can be issued. For more information on generating DMA requests, refer to Section 23.5.6.1.2, “Setting up the UART to Request DMA Service,” and Section 16.2, “DMA Request Control (DMAREQC).”

Table 23-12briefly describes the UART module signals.

NOTE

The terms ‘assertion’ and ‘negation’ are used to avoid confusion between active-low and active-high signals. ‘Asserted’ indicates that a signal is active, independent of the voltage level; ‘negated’ indicates that a signal is inactive.

MOTOROLA Chapter 23. UART Modules 23-17