Motorola MCF5282, MCF5281 user manual Mode Register Settings

SDRAM Controller Operation

15.2.4.1Mode Register Settings

It is possible to configure the operation of SDRAMs, namely their burst operation and CAS latency, through the SDRAM component’s mode register. CAS latency is a function of the speed of the SDRAM and the bus clock of the DRAM controller. The DRAM controller operates at a CAS latency of 1, 2, or 3.

Although the MCF5282 DRAM controller supports bursting operations, it does not use the bursting features of the SDRAMs. Because the MCF5282 can burst operand sizes of 1, 2, 4, or 16 bytes long, the concept of a fixed burst length in the SDRAMs mode register becomes problematic. Therefore, the MCF5282 DRAM controller generates the burst cycles rather than the SDRAM device. Because the MCF5282 generates a new address and a READ or WRITE command for each transfer within the burst, the SDRAM mode register should be set either not to burst or to a burst length of one. This allows bursting to be controlled by the MCF5282.

The SDRAM mode register is written by setting the associated block’s DACR[IMRS]. First, the base address and mask registers must be set to the appropriate configuration to allow the mode register to be set. Note that improperly set DMR mask bits may prevent access to the mode register address. Thus, the user should determine the mapping of the mode register address to the MCF5282 address bits to find out if an access is blocked. If the DMR setting prohibits mode register access, the DMR should be reconfigured to enable the access and then set to its necessary configuration after the MRS command executes.

The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next access to the SDRAM address space generates the MRS command to that SDRAM. The address of the access should be selected to place the correct mode information on the SDRAM address pins. The address is not multiplexed for the MRS command. The MRS access can be a read or write. The important thing is that the address output of that access needs the correct mode programming information on the correct address bits.

Figure 15-10shows the MRS command, which occurs in the first clock of the bus cycle.

15-18 MCF5282 User’s Manual MOTOROLA