Motorola MCF5281 Chip Select Module Signals, 1lists signals used by the chip select module

Chapter 12

Chip Select Module

This chapter describes the MCF5282 chip select module, including the operation and programming model of the chip select registers, which include the chip select address, mask, and control registers.

NOTE

Unless otherwise noted, in this chapter, “clock” refers to the

CLKOUT used for the bus.

12.1 Overview

The following list summarizes the key chip select features:

•Up to seven independent, user-programmable chip select signals (CS[6:0]) that can interface with external SRAM, PROM, EPROM, EEPROM, Flash, and peripherals

•Address masking for 64-Kbyte to 4-Gbyte memory block sizes

12.2 Chip Select Module Signals

Table 12-1lists signals used by the chip select module.

			Table 12-1. Chip Select Module Signals
Signal			Description
Chip Selects	Each		can be independently programmed for an address location as well as for masking, port
		CSn
(CS[6:0])	size, read/write burst capability, wait-state generation, and internal/external termination. Only CS0 is
	initialized at reset and may act as an external boot chip select to allow boot ROM to be at an external
	address space. Port size for CS0 is configured by the logic levels of D[19:18] when RSTO negates
	and RCON is asserted.
Output Enable	Interfaces to memory or to peripheral devices and enables a read transfer. It is asserted and negated
(OE)	on the falling edge of the clock. OE is asserted only when one of the chip selects matches for the
	current address decode.
Byte Strobes	These signals are individually programmed through the byte-enable mode bit, CSCRn[BEM],
BS[3:0]	described in Section 12.4.1.3.
	These generated signals provide byte data select signals, which are decoded from the transfer size,
	A1, and A0 signals in addition to the programmed port size and burstability of the memory accessed,
	as Table 12-2shows.

MOTOROLA Chapter 12. Chip Select Module 12-1