Motorola MCF5281, MCF5282 user manual Clock Module, Interrupt Controller Modules

	CONTENTS
Paragraph	Title	Page
Number		Number
	Chapter 9
	Clock Module
9.1	Features	9-1
9.2	Modes of Operation	9-1
9.2.1	Normal PLL Mode	9-1
9.2.2	1:1 PLL Mode	9-2
9.2.3	External Clock Mode	9-2
9.3	Low-power Mode Operation	9-2
9.4	Block Diagram	9-3
9.5	Signal Descriptions	9-4
9.5.1	EXTAL	9-4
9.5.2	XTAL	9-5
9.5.3	CLKOUT	9-5
9.5.4	CLKMOD[1:0]	9-5
9.5.5	RSTOUT	9-5
9.6	Memory Map and Registers	9-5
9.6.1	Module Memory Map	9-5
9.6.2	Register Descriptions	9-6
9.7	Functional Description	9-10
9.7.1	System Clock Modes	9-10
9.7.2	Clock Operation During Reset	9-11
9.7.3	System Clock Generation	9-11
9.7.4	PLL Operation	9-12
	Chapter 10
	Interrupt Controller Modules
10.1	68K/ColdFire Interrupt Architecture Overview	10-1
10.1.1	Interrupt Controller Theory of Operation	10-3
10.2	Memory Map	10-5
10.3	Register Descriptions	10-6
10.3.1	Interrupt Pending Registers (IPRHn, IPRLn)	10-6
10.3.2	Interrupt Mask Register (IMRHn, IMRLn)	10-8
10.3.3	Interrupt Force Registers (INTFRCHn, INTFRCLn)	10-9
10.3.4	Interrupt Request Level Register (IRLRn)	10-10
10.3.5	Interrupt Acknowledge Level and Priority Register (IACKLPRn)	10-11
10.3.6	Interrupt Control Register (ICRnx, (x = 1, 2,..., 63))	10-11

10.3.7Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK).10-15

10.4	Prioritization Between Interrupt Controllers	10-16
10.5	Low-Power Wakeup Operation	10-17

MOTOROLA Contents ix