DMA Controller Module Functional Description

16.5.3 Channel Initialization and Startup

Before a block transfer starts, channel registers must be initialized with information describing configuration, request-generation method, and the data block.

16.5.3.1Channel Prioritization

The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel 3 having the lowest) or in an order determined by DCRn[BWC]. If the BWC encoding for a DMA channel is 000, that channel has priority only over the channel immediately preceding it. For example, if DCR3[BWC] = 000, DMA channel 3 has priority over DMA channel 2 (assuming DCR2[BWC] ≠ 000) but not over DMA channel 1.

If DCR0[BWC] = DCR1[BWC] = 000, DMA0 still has priority over DMA1. In this case, DCR1[BWC] = 000 does not affect prioritization.

Simultaneous external requests are prioritized either in ascending order or in an order determined by each channel’s DCRn[BWC] bits.

16.5.3.2Programming the DMA Controller Module

Note the following general guidelines for programming the DMA:

No mechanism exists within the DMA module itself to prevent writes to control registers during DMA accesses.

If the DCRn[BWC] value of sequential channels are equal, the channels are prioritized in ascending order.

The SARn is loaded with the source (read) address. If the transfer is from a peripheral device to memory, the source address is the location of the peripheral data register. If the transfer is from memory to either a peripheral device or memory, the source address is the starting address of the data block. This can be any aligned byte address.

The DARn should contain the destination (write) address. If the transfer is from a peripheral device to memory, or from memory to memory, the DARn is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, DARn is loaded with the address of the peripheral data register. This address can be any aligned byte address.

SARn and DARn change after each cycle depending on DCRn[SSIZE,DSIZE, SINC,DINC] and on the starting address. Increment values can be 1, 2, 4, or 16 for byte, word, longword, or 16-byte line transfers, respectively. If the address register is programmed to remain unchanged (no count), the register is not incremented after the data transfer.

MOTOROLA

Chapter 16. DMA Controller Module

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Motorola MCF5281 Channel Initialization and Startup, Channel Prioritization, Programming the DMA Controller Module