Motorola MCF5281, MCF5282 MII Management Frame Register Mmfr, ECR Field Descriptions, Data

			Programming Model
	Table 17-16. ECR Field Descriptions
Bits	Name		Description
31-2	—	Reserved.
1	ETHER_EN	When this bit is set, the FEC is enabled, and reception and
		transmission are possible. When this bit is cleared, reception is
		immediately stopped and transmission is stopped after a bad CRC
		is appended to any currently transmitted frame. The buffer
		descriptor(s) for an aborted transmit frame are not updated after
		clearing this bit. When ETHER_EN is deasserted, the DMA, buffer
		descriptor, and FIFO control logic are reset, including the buffer
		descriptor and FIFO pointers. The ETHER_EN bit is altered by
		hardware under the following conditions:
		•	ECR[RESET] is set by software, in which case ETHER_EN will
			be cleared
		•	An error condition causes the EIR[EBERR] bit to set, in which
			case ETHER_EN will be cleared
0	RESET	When this bit is set, the equivalent of a hardware reset is
		performed but it is local to the FEC. ETHER_EN is cleared and all
		other FEC registers take their reset values. Also, any
		transmission/reception currently in progress is abruptly aborted.
		This bit is automatically cleared by hardware during the reset
		sequence. The reset sequence takes approximately 8 system
		clock cycles after RESET is written with a 1.

17.5.4.6 MII Management Frame Register (MMFR)

The MMFR is accessed by the user and does not reset to a defined value. The MMFR register is used to communicate with the attached MII compatible PHY device(s), providing read/write access to their MII registers. Performing a write to the MMFR will cause a management frame to be sourced unless the MSCR has been programmed to 0. In the case of writing to MMFR when MSCR = 0, if the MSCR register is then written to a non-zero value, an MII frame will be generated with the data previously written to the MMFR. This allows MMFR and MSCR to be programmed in either order if MSCR is currently zero.

Field

Reset

R/W

Field

Reset

R/W Address

31	30	29	28	27	23	22	18	17	16
	ST		OP		PA		RA	TA
					Undefined
					R/W
15									0

DATA

Undefined

R/W

IPSBAR + 0x1040

Figure 17-9. MII Management Frame Register (MMFR)

MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-29