ILLUSTRATIONS

Figure

Title

Page

Number

Number

 

13-4

Data Transfer State Transition Diagram

13-5

13-5

Read Cycle Flowchart

13-7

13-6

Basic Read Bus Cycle

13-7

13-7

Write Cycle Flowchart

13-8

13-8

Basic Write Bus Cycle

13-8

13-9

Read Cycle with Fast Termination

13-9

13-10

Write Cycle with Fast Termination

13-9

13-11

Back-to-Back Bus Cycles

13-10

13-12

Line Read Burst (2-1-1-1), External Termination

13-11

13-13

Line Read Burst (2-1-1-1), Internal Termination

13-12

13-14

Line Read Burst (3-2-2-2), External Termination

13-12

13-15

Line Read Burst-Inhibited, Fast Termination, External Termination

13-13

13-16

Line Write Burst (2-1-1-1), Internal/External Termination

13-13

13-17

Line Write Burst (3-2-2-2) with One Wait State

13-14

13-18

Line Write Burst-Inhibited

13-14

13-19

Example of a Misaligned Longword Transfer (32-Bit Port)

13-15

13-20

Example of a Misaligned Word Transfer (32-Bit Port)

13-15

14-1

MCF5282 Block Diagram with Signal Interfaces

14-2

15-1

Synchronous DRAM Controller Block Diagram

15-2

15-2

DRAM Control Register (DCR)

15-5

15-3

DRAM Address and Control Register (DACRn)

15-6

15-4

DRAM Controller Mask Registers (DMRn)

15-8

15-5

Connections for External Memory Port Sizes

15-13

15-6

Burst Read SDRAM Access

15-14

15-7

Burst Write SDRAM Access

15-15

15-8

Auto-Refresh Operation

15-16

15-9

Self-Refresh Operation

15-17

15-10

Mode Register Set (mrs) Command

15-19

15-11

Initialization Values for DCR

15-20

15-12

SDRAM Configuration

15-21

15-13

DACR Register Configuration

15-21

15-14

DMR0 Register

15-22

16-1

DMA Signal Diagram

16-2

16-2

DMA Request Control Register (DMAREQC)

16-3

16-3

Dual-Address Transfer

16-4

16-4

Source Address Registers (SARn)

16-6

16-5

Destination Address Registers (DARn)

16-6

16-6

Byte Count Registers (BCRn)—BCR24BIT = 1

16-7

16-7

Byte Count Registers (BCRn)—BCR24BIT = 0

16-7

16-8

DMA Control Registers (DCRn)

16-8

16-9

DMA Status Registers (DSRn)

16-10

17-1

FEC Block Diagram

17-4

17-2

Ethernet Address Recognition—Receive Block Decisions

17-12

 

 

 

MOTOROLA

Illustrations

xxv

Page 25
Image 25
Motorola MCF5281, MCF5282 user manual 13-4