Motorola MCF5282 Fifo Receive Start Register Frsr, Receive Descriptor Ring Start Erdsr, Rfstart

Programming Model

17.5.4.20 FIFO Receive Start Register (FRSR)

The FRSR is an 8-bit register programmed by the user to indicate the starting address of the receive FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses from the start of the FIFO to the location four bytes before the address programmed into the FRSR. The receive FIFO uses addresses from FRSR to FRBR inclusive.

The FRSR register is initialized by hardware at reset. FRSR only needs to be written to change the default value.

Field

Reset

R/W

Field

Reset

R/W Address

31 16

—

0000_0000_0000_0000

R

15	10	9	2	1	0
	—		R_FSTART		—

0000_0101_0000_0000

R

IPSBAR + 0x1150

Figure 17-23. FIFO Receive Start Register (FRSR)

Table 17-32. FRSR Field Descriptions

Bits	Name	Descriptions
31–10	—	Reserved, read as 0 (except bit 10, which is read as 1).
9–2	R_FSTART	Address of first receive FIFO location. Acts as delimiter
		between receive and transmit FIFOs.
1–0	—	Reserved, read as 0.

17.5.4.21 Receive Descriptor Ring Start (ERDSR)

The ERDSR is written by the user. It provides a pointer to the start of the circular receive buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16).

This register is not reset and must be initialized by the user prior to operation.

17-42 MCF5282 User’s Manual MOTOROLA