Motorola MCF5281, MCF5282 user manual Sram Features, Sram Operation, Sram Programming Model

Chapter 5

Static RAM (SRAM)

5.1SRAM Features

•One 64-Kbyte SRAM

•Single-cycle access

•Physically located on processor's high-speed local bus

•Memory location programmable on any 0-modulo-64 Kbyte address

•Byte, word, longword address capabilities

5.2SRAM Operation

The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a single cycle. The location of the memory block can be specified to any 0-modulo-64K address within the 4-GByte address space. The memory is ideal for storing critical code or data structures or for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can service processor-initiated access or memory-referencing commands from the debug module.

Depending on configuration information, instruction fetches may be sent to both the cache and the SRAM block simultaneously. If the reference is mapped into the region defined by the SRAM, the SRAM provides the data back to the processor, and the cache data discarded. Accesses from the SRAM module are not cached.

The SRAM is dual-ported to provide DMA access. The SRAM is partitioned into two physical memory arrays to allow simultaneous access to both arrays by the processor core and another bus master. See Chapter 5, “System Control Module (SCM)” for more information.

5.3SRAM Programming Model

The SRAM programming model includes a description of the SRAM base address register (RAMBAR), SRAM initialization, and power management.

MOTOROLA Chapter 5. Static RAM (SRAM) 5-1