Motorola MCF5282, MCF5281 user manual Gpio Registers

Table A-3. Register Memory Map (Continued)

Address	Name	Mnemonic	Size
IPSBAR + 0x10E4	Physical Address Low	PALR	32
IPSBAR + 0x10E8	Physical Address High+ Type Field	PAUR	32
IPSBAR + 0x10EC	Opcode + Pause Duration	OPD	32
IPSBAR + 0x1118	Upper 32 bits of individual hash table	IAUR	32
IPSBAR + 0x111C	Lower 32 bits of individual hash table	IALR	32
IPSBAR + 0x1120	Upper 32-bits of group hash table	GAUR	32
IPSBAR + 0x1124	Lower 32-bits of group hash table	GALR	32
IPSBAR + 0x1144	Transmit FIFO Watermark	TFWR	32
IPSBAR + 0x114C	FIFO Receive Bound Register	FRBR	32
IPSBAR + 0x1150	FIFO Receive Start Address	FRSR	32
IPSBAR + 0x1180	Pointer to Receive Descriptor Ring	ERDSR	32
IPSBAR + 0x1184	Pointer to Transmit Descriptor Ring	ETDSR	32
IPSBAR + 0x1188	Maximum Receive Buffer Size	EMRBR	32
IPSBAR +	RAM used to store management counters	MIB_RAM	32
0x1200-0x13FF
	GPIO Registers
IPSBAR +	Port A Output Data Register	PORTA	8
0x10_0000
IPSBAR +	Port B Output Data Register	PORTB	8
0x10_0001
IPSBAR +	Port C Output Data Register	PORTC	8
0x10_0002
IPSBAR +	Port D Output Data Register	PORTD	8
0x10_0003
IPSBAR +	Port E Output Data Register	PORTE	8
0x10_0004
IPSBAR +	Port F Output Data Register	PORTF	8
0x10_0005
IPSBAR +	Port G Output Data Register	PORTG	8
0x10_0006
IPSBAR +	Port H Output Data Register	PORTH	8
0x10_0007
IPSBAR +	Port J Output Data Register	PORTJ	8
0x10_0008
IPSBAR +	Port DD Output Data Register	PORTDD	8
0x10_0009
IPSBAR +	Port EH Output Data Register	PORTEH	8
0x10_000A
IPSBAR +	Port EL Output Data Register	PORTEL	8
0x10_000B

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