Motorola MCF5281, MCF5282 user manual Auto-Refresh Operation, Burst Write Sdram Access

SDRAM Controller Operation

CLKOUT

A[31:0]

SRAS

SCAS

DRAMW

D[31:0]

SDRAM_CS[0] or [1]

BS[3:0]

Row Column Column Column Column

tRP

tCASL = 2 tRWL

ACTV NOP WRITE WRITE WRITE WRITE NOP PALL

Figure 15-7. Burst Write SDRAM Access

Accesses in synchronous burst page mode always cause the following sequence:

1.ACTV command

2.NOP commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no NOP commands).

3.Required number of READ or WRITE commands to service the transfer size with the given port size.

4.Some transfers need more NOP commands to assure the ACTV-to-precharge delay.

5.PALL command

6.Required number of idle clocks inserted to assure precharge-to-ACTVdelay.

15.2.3.5Auto-Refresh Operation

The DRAM controller is equipped with a refresh counter and control. This logic is responsible for providing timing and control to refresh the SDRAM without user interaction. Once the refresh counter is set, and refresh is enabled, the counter counts to zero. At this time, an internal refresh request flag is set and the counter begins counting down again. The DRAM controller completes any active burst operation and then performs a PALL operation. The DRAM controller then initiates a refresh cycle and clears the refresh

MOTOROLA Chapter 15. Synchronous DRAM Controller Module 15-15