Motorola MCF5281, MCF5282 user manual Index-11

INDEX

FLASHBAR, 2-8,6-5protection (CFMPROT), 6-12security (CFMSEC), 6-10supervisor access (CFMSACC), 6-13user status (CFMUSTAT), 6-15

core

address (An), 2-3

condition code (CCR), 2-4,2-4data (Dn), 2-3

stack pointer (A7), 2-3,2-7status register (SR), 2-6vector base (VBR), 2-8

debug

address attribute trigger (AATR), 29-8address breakpoint (ABLR, ABHR), 29-9configuration/status (CSR), 29-10

data breakpoint/mask (DBR, DBMR), 29-12

program counter breakpoint/mask (PBR/PBMR), 29-13

trigger definition (TDR), 29-14DMA controller

byte count (BCRn), 16-7control (DCRn), 16-8destination address (DARn), 16-6request control (DMAREQC), 16-3source address (SARn), 16-6status (DSRn), 16-10

DMA timers

capture (DTCRn), 21-7counters (DTCNn), 21-8event (DTERn), 21-6mode (DTMRn), 21-4reference (DTRRn), 21-7

EMAC

mask (MASK), 3-11status (MACSR), 3-6

EPORT

data direction (EPDDR), 11-4flag (EPFR), 11-6

pin assignment (EPPAR), 11-4pin data (EPPDR), 11-6

port data (EPDR), 11-5

port interrupt enable (EPIER), 11-5Ethernet

control (ECR), 17-28

descriptor group upper/lower address (GAUR/GALR), 17-39

descriptor individual upper/lower (IAUR/IALR), 17-38

descriptor individual upper/lower address (IAUR/IALR), 17-37

FIFO receive bound (FRBR), 17-41FIFO receive start (FRSR), 17-42

FIFO transmit FIFO watermark (TFWR), 17-40interrupt event (EIR), 17-23

interrupt mask (EIMR), 17-26MIB control (MIBC), 17-32

MII management frame (MMFR), 17-29MII speed control (MSCR), 17-31opcode/pause duration (OPD), 17-37physical address low, 17-35

physical address low/high (PALR, PAUR), 17-35receive buffer size (EMRBR), 17-44

receive control (RCR), 17-33

receive descriptor active (RDAR), 17-26receive descriptor ring start (ERDSR), 17-42registers

transmit buffer descriptor ring start (ETSDR), 17-43

transmit control (TCR), 17-34

transmit descriptor active (TDAR), 17-27

FEC

physical address low, 17-35FlexCAN

control 0–2 (CANCTRLn), 25-22–25-25error and status (ESTAT), 25-28

free running timer (TIMER), 25-26interrupt flag (IFLAG), 25-31interrupt mask (IMASK), 25-30module configuration (CANMCR), 25-20prescaler divide (PRESDIV), 25-24receive error counter (RXECTR), 25-32

receive mask (RXGMASK, RXnMASK), 25-27transmit error counter (TXECTR), 25-32

general purpose timers channel (GPTCn), 20-13compare force (GPCFORC), 20-6control 1–2 (GPTCTLn), 20-9counter (GPTCNT), 20-7

flag 1–2 (GPTFLGn), 20-12

input capture/output compare select (GPTIOS), 20-5

interrupt enable (GPTIE), 20-10

output compare 3 data (GPTOC3D), 20-7output compare 3 mask (GPTOC3M), 20-6port data (PORTTn), 20-16

port data direction (GPTDDR), 20-16

pulse accumulator control (GPTPACTL), 20-13pulse accumulator counter (GPTPACNT), 20-15pulse accumulator flag (GPTPAFLG), 20-14system control 1–2 (GPTSCRn), 20-8,20-11toggle-on-overflow (GPTTOV), 20-9

GPIO

port AS pin assignment (PASPAR), 26-19port B/C/D pin assignment (PBCDPAR), 26-14port clear output data (CLRn), 26-12

port data direction (DDRn), 26-9

port E pin assignment (PEPAR), 26-15

port EH/EL pin assignment (PEHLPAR), 26-20port F pin assignment (PFPAR), 26-17

MOTOROLA MCF5282 User’s Manual Index-11