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Motorola MCF5281, MCF5282 user manual Revision Date Substantive Changes, Number Release, Frsr

Models: MCF5282 MCF5281

1 816

Page 53

								Revision History
				Table iii. Revision History

Revision	Date of						Substantive Changes	Section/Page
Number	Release						Substantive Changes	Section/Page
Number	Release

		Changed text in Step 1 to read “If fSYS ⎟ 2 is greater than 12.8 MHz,						6.4.3.1/6-18
		PRDIV8 = 1; otherwise PRDIV8 = 0.”

		Changed equation in Step 2 to the following:						6.4.3.1/6-18
			DIV[5:0] =				fSYS
			DIV[5:0] =				2 x 200kHz x (1 + (PRDIV8 x 7))
							2 x 200kHz x (1 + (PRDIV8 x 7))

		Changed equation in Step 3 to the following:						6.4.3.1/6-18
		fCLK =					fSYS
		fCLK =				2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7))
		Changed equations in example to reflect revisions above.						6.4.3.1/6-18

		Changed text to read “So, for fSYS = 66 MHz, writing 0x54 to CFMCLKD						6.4.3.1/6-18
		will set FCLK to 196.43 kHz which is a valid frequency for the timing of
		program and erase functions.”

		Changed text to read “Consider the follwoing example for fSYS = 66 MHz.”						6.4.3.1/6-18
		Added “Page erase verify” category.						Table 6-12/6-16

		Added “Page erase verify” category and description.						Table 6-13/6-20

		Added “Access error” row.						Table 6-14/6-25

		Moved information in Section 8.4.6, “DMA Request Control Register,” to						Chapter 8 and
		Section 16.2, “DMA Request Control (DMAREQC).”						16.2/16-3

		Changed offset for the copy of RAMBAR to “0x008.”						Figure 8-2/8-5

		Changed CWTIC to CWTIF.						Table 8-5/8-8

		Changed text to read “Setting MPARK[PRK_LAST] causes the arbitration						8.5.2.1/8-11
		pointer to be parked on the highest priority master.”

		Changed “⎟ MFD (2–9)” to “⎟ MFD (4–18).”						Figure 9-2/9-4

		Changed equation in “Normal PLL Clock Mode” row to the following:						Table 9-7/9-11
		fsys = fref ⋅ 2(MFD + 2)/2RFD
		Eliminated Section 12.4.1.4, “Code Example.”						Chapter 12

		In “Reset: CSCR0” row, changed “D7, D6, D5” to “—, D19, D18.”						Figure 12-4/12-8

		Replaced			with “SCKE.”			Table 14-1/14-3
		Replaced	“SCKE”		with “SCKE.”			Table 14-1/14-3

		Changed text to read “The transmit FIFO uses addresses from the start of the						17.5.4.20/17-42
		FIFO to the location four bytes before the address programmed into the
		FRSR.”

		Added the following footnote: “The receive buffer pointer, which contains the						Table 17-36/17-48
		address of the associated data buffer, must always be evenly divisible by 16.
		The buffer must reside in memory external to the FEC. This value is never
		modified by the Ethernet controller.”

		Added the following footnote: “The transmit buffer pointer, which contains						Table 17-37/17-50
		the address of the associated data buffer, must always be evenly divisible by
		4. The buffer must reside in memory external to the FEC. This value is never
		modified by the Ethernet controller.”

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Motorola MCF5281, MCF5282 user manual Revision Date Substantive Changes, Number Release, Frsr

Contents

MCF5282 ColdFire Microcontroller User’s Manual HOW to Reach US USA/EUROPE/LOCATIONS not Listed IND IND Contents Timing Assumptions Move Instruction Execution Times Chapter Enhanced Multiply-Accumulate Unit EmacColdFire Flash Module CFM Chapter CacheChapter Static RAM Sram Chapter System Control Module SCM Chapter Power ManagementInterrupt Controller Modules Clock ModuleChapter Edge Port Module Eport Signal DescriptionsChapter Chip Select Module Chapter External Interface Module EIMChapter DMA Controller Module Chapter Synchronous Dram Controller ModuleChapter Fast Ethernet Controller FEC Chapter General Purpose Timer Modules Gpta and Gptb Chapter Watchdog Timer ModuleChapter Programmable Interrupt Timer Modules PIT0-PIT3 20.3 Chapter Queued Serial Peripheral Interface Qspi Module Chapter DMA Timers DTIM0-DTIM3Chapter I2C Interface Chapter Uart ModulesChapter FlexCAN Chapter Queued Analog-to-Digital Converter Qadc Chapter General Purpose I/O Module27.4.7 Chapter Debug Support Reset Controller ModuleChapter Ieee 1149.1 Test Access Port Jtag Chapter Chip Configuration Module CCMChapter Mechanical Data Electrical CharacteristicsAppendix a Register Memory Map Paragraph Title Number 31.6.2 Nonscan Chain Operation 31-12Title Number Illustrations10-7 13-4 17-13 20-20 23-10 25-31 Qadc Status Register 0 QASR0 27-22 27-12 27-53 29-39WDMREG BDM Command Format 29-36 29-40 Tables Charge Pump Current and MFD in Normal Mode Operation 10-13 15-18 17-30 20-23 25-21 27-13 29-43 33-21 Timer Module AC Timing Specifications 33-24 33-22 Organization AudienceOrganization Xlv ColdFire Documentation Suggested ReadingGeneral Information Conventions Meaning Acronyms and AbbreviationsTable i. Acronyms and Abbreviated Terms Table ii. Notational Conventions Terminology ConventionsOperand Syntax Opcode WildcardCCR ACCPort Name PSTMSW LSWTable iii provides a revision history for this document Revision HistoryTable iii. Revision History SSTFrsr Revision Date Substantive ChangesNumber Release Liv RAMBAR.’ 10.3.6/10-11Substantive Changes Section/Page Revision NumberChapter Overview MCF5282 Key FeaturesMCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Key Features MCF5282 Block Diagram Configuration Tag Address Data Array Address Cache ConfigurationVersion 2 ColdFire Core CacheDebug Module SramFlash External Interface Module EIM System Control ModuleChip Select Power ManagementGeneral Input/Output Ports Interrupt Controllers INTC0/INTC1Uart Modules Test Access PortPeriodic Interrupt Timers PIT0-PIT3 DMA Timers DTIM0-DTIM3General-Purpose Timers GPTA/GPTB Phase Locked Loop PLL Software Watchdog TimerReset DMA ControllerMCF5282-Specific Features MCF5282-Specific Features IAG Processor PipelinesFifo DsocUser Programming Model Processor Register DescriptionAddress Registers A0-A6 Data Registers D0-D7Stack Pointer A7 Program Counter PCBits Name Description Condition Code Register CCRSupervisor Programming Model Emac Programming ModelBits Status Register SRSystem Byte Condition Code Register CCR Supervisor/User Stack Pointers A7 and OTHERA7 Programming Model Access Control Registers ACR0, ACR1Vector Base Register VBR Cache Control Register CacrLocal Memory Registers Additions to the Instruction Set ArchitectureName CPU Space Rc Written with Register Name Instruction Description Exception Processing OverviewISA Revision A+ New Instructions Vector Stacked Program Assignment NumberS Offset Hex Counter Exception Vector Assignments0x100-0x3FC Next Exception Stack Frame DefinitionFormat Field Encodings Fault Status Encodings Access Error ExceptionProcessor Exceptions FS30 DefinitionIllegal Instruction Exception Address Error ExceptionDivide-By-Zero Privilege ViolationDebug Interrupt Unimplemented Line-A OpcodeUnimplemented Line-F Opcode Fault-on-Fault Halt RTE and Format Error ExceptionReset Exception Trap Instruction ExceptionMAC DIV Emac FPU MMU ISA Debug VER REVMAC D0 Hardware Configuration Info Field DescriptionVER ICA ICA Icsiz RAM0SIZ ROM0SIZBusw DCA Dcsiz RAM1SIZ ROM1SIZ 8KB RAM 4KB RAM16KB RAM 32KB RAMTiming Assumptions Instruction Execution TimingAddress10 Size Kbus Additional Operations CR/W Move Instruction Execution Times10. Misaligned Operand References Source Destination Ax+ D16,Ax D8,Ax,Xi Xxx.wl 11. Move Byte and Word Execution Times12. Move Long Execution Times Standard Two Operand Instruction Execution Times Standard One Operand Instruction Execution Times13. One Operand Instruction Execution Times 14. Two Operand Instruction Execution TimesStandard Two Operand Instruction Execution Times 15. Miscellaneous Instruction Execution Times Miscellaneous Instruction Execution TimesEffective Address Opcode An+ D16,An D8,An,Xn*SF Xxx.wl D16,PC D8,PC,Xn*SFEffective Address Opcode An+ D16,An D8,An,X Xxx.wl #xxx Emac Instruction Execution Times16. Emac Instruction Execution Times ColdFire Instruction Set Architecture Enhancements Branch Instruction Execution Times17. General Branch Instruction Execution Times 18. BRA, Bcc Instruction Execution TimesAssembler Syntax OperationAttributes Instruction FormatCondition Codes Byte Reverse Register ByterevAssembler Syntax BYTEREV.L Dx Attributes Old Dx310 New Dx310 Find First One in RegisterAssembler SyntaxSTRLDSR #data Store/Load Status Register StrldsrSupported Starting with ISA A+ Multiply-Accumulate Unit Chapter Enhanced Multiply-Accumulate Unit EmacIntroduction to the MAC Multiply-Accumulate Functionality DiagramInfinite Impulse Response IIR Filter General OperationFractional Alignment Motorola 1describes Macsr fields Memory Map/Register SetMAC Status Register Macsr Macsr Field Descriptions Rounding Fractional Operation ModeSummary of S/U, F/I, and R/T Control Bits Operational ModesSaving and Restoring the Emac Programming Model MULS/MULU Following code performs the Emac state restoreMask Register Mask MAC.sz Ry,RxSF,eay&,Rw Emac Instruction Set Summary Command Mnemonic DescriptionEmac Instruction Execution Times 3summarizes Emac unit instructionsAccumulator Mac Old Mov New Data RepresentationMac Mov Two’s Complement, Signed Fractional Equation MAC OpcodesMACSR.V = Emac Instruction Set Summary MACSR.Z = Emac Instruction Set Summary Motorola Emac Instruction Set Summary MCF5282 User’s Manual This chapter describes the MCF5282 cache operation Cache FeaturesCache Physical Organization Cache Physical Organization Interaction with Other Modules Cache OperationCache Coherency and Invalidation Memory Reference AttributesCLNF10 Longword Address Bits Cache Miss Fetch Algorithm/Line FillsInitial Fetch Offset vs. Clnf Bits CACR31 CACR10 Type of Instruction Fetch Description Instruction Cache Operation as Defined by CACR31Cache Registers Memory Map Cache Programming ModelCache Registers Cache Control Register CacrCinv Didi Disd Invi Invd Cenb CPDCeib DCM Dbwe DWP Eusp Clnf CenbCeib CACR31 CACR23 CACR22 Configuration Description Cache Configuration as Defined by CACR31, 23CACR23 CACR22 CACR21 CACR20 Configuration Operation Cache Invalidate All as Defined by CACR23, 22, 21Bufw Access Control Registers ACR0, ACR1External Fetch Size Based on Miss Address and Clnf Between the processors local bus and the external bus BWESram Programming Model Sram FeaturesSram Operation PRI1 PRI2 SPV Sram Base Address Register RambarPRI1, PRI2 PRI12 Upper Bank Lower Bank PrioritySram Base Address Register Sram InitializationTypical Rambar Setting Examples Power ManagementSram Initialization Code Following loop initializes the entire Sram to zeroSram Programming Model Sram Programming Model MCF5282 User’s Manual Chapter ColdFire Flash Module CFM FeaturesBlock Diagram CFM Block Diagram CFM Array Memory Map Memory MapCFM Configuration Field CFM Configuration FieldFlash Base Address Register Flashbar Address Offset from array base Size DescriptionMemory Map BA30 BA29 CFM Registers CFM Configuration Register CfmcrRegister Descriptions Flash registers are described in this subsectionCfmcr Field Descriptions CFM Clock Divider Register CfmclkdBits Name Description Divld PRDIV8Cfmclkd Field Descriptions CFM Security Register CfmsecSEC150 Description Cfmsec Field DescriptionsProt CFM Protection Register CfmprotCfmprot Field Descriptions PROTECT31 CFM Supervisor Access Register CfmsaccPROTECT2 SectorData CFM Data Access Register CfmdaccCfmsacc Field Descriptions Only one Cfmustat bit should be cleared at a time CFM User Status Register Cfmustat10. Cfmustat Field Descriptions Cbeif Ccif Pviol Accerr BlankCommand Name Description CFM Command Register Cfmcmd12. Cfmcmd User Mode Commands Read Operations CFM OperationWrite Operations Program and Erase OperationsConsider the following example for fSYS = 66 MHz Setting the Cfmclkd RegisterThus the Flash state machine clock will be Program, Erase, and Verify Sequences 13summarizes the valid Flash user commands Flash Valid Commands13. Flash User Commands Meaning Description13. Example Program Algorithm Flash User Mode Illegal Operations Stop ModeFlash Security Operation Master ModeErase Verify Check ResetBack Door Access Interrupts Interrupt Source Interrupt Flag Local Enable14. CFM Interrupt Sources Cbeif CbeieInterrupts MCF5282 User’s Manual Programming Model Memory Map and RegistersChip Configuration Module Memory Map Low-Power Interrupt Control Register LpicrMemory Map Following subsection describes the PMM registersEnbstop Lpicr Field DescriptionXlpmipl Settings Low-Power Control Register LpcrXlpmipl Interrupts Level Needed to Exit Low-Power Mode Lpmd Stpmd LvdseLow-Power Modes Low-Power ModesPLL/CLKOUT Stop Mode Operation Functional DescriptionWait Mode Run ModeDoze Mode Stop ModeStatic Random-Access Memory Sram Peripheral Behavior in Low-Power ModesPeripheral Shut Down ColdFire CoreChip Select Module Sdram Controller SdramcDMA Controller DMAC0-DMA3 Uart Modules UART0, UART1, and UART2Queued Serial Peripheral Interface Qspi DMA Timers DMAT0-DMAT32.9 I2C Module Interrupt Controllers INTC0, INTC1 Reset ControllerFast Ethernet Controller FEC 2.14 I/O PortsClock Module Chip Configuration ModuleProgrammable Interrupt Timers PIT0, PIT1, PIT2 and PIT3 Watchdog TimerEdge Port Queued Analog-to-Digital Converter QadcFlexCAN General Purpose Timers Gpta and GptbFunctional Description ColdFire Flash Module CPU and Peripherals in Low-Power Modes Summary of Peripheral State During Low-Power Modes2.25 BDM JtagJtag QadcBDM Functional Description MCF5282 User’s Manual Overview Features3124 2316 158 Memory Map and Register DefinitionSCM Register Map Cache Register DescriptionsInternal Peripheral System Base Address Register Ipsbar Ipsbar Field Description Memory Base Address Register RambarBDE Memory Base Address Register Rambar Rambar Field DescriptionCrsr Field Descriptions Core Reset Status Register CrsrCore Watchdog Control Register Cwcr Register Descriptions CWT CWT Time-Out Period Core Watchdog Timer DelayInternal Bus Arbitration Core Watchdog Service Register CwsrFEC Sdramc SRAM1 Mpark Rambar CPU DMA EIMMarb Arbitration Algorithms Round-Robin ModeOverview Fixed Timeout Prklast Lckouttime Fixed ModeBus Master Park Register Mpark M2PEN BCR24BIT M3PRTY M2PRTY M0PRTY M1PRTYMpark Field Description Features System Access Control Unit SacuSacu Register Memory Map Memory Map/Register Definition3128 2724 2320 1916 1512 118 PACR1 PACR2 PACR3PACR6 Peripheral Access Control Registers Pacr 0-PACR8Master Privilege Register MPR Ipsbar Offset Name Modules Controlled 12. Peripheral Access Control Registers PACRsBits Supervisor Mode User Mode Qspi UART2DTIM0 DTIM1 DTIM2 DTIM3Gpacr Field Descriptions 13. Grouped PeripheralAccess Control Register14. Gpacr Accessctrl Bit Encodings Register Space Protected Modules Protected Ipsbar Offset 15. Gpacr Address SpaceGPACR0 EPORT, WDOG, PIT0-PIT3, QADC, GPTA, GptbModes of Operation Normal PLL Mode2 11 PLL Mode Low-power Mode OperationExternal Clock Mode Clock Module Operation in Low-power ModesClock Module Block Diagram Block DiagramSignal Properties Signal DescriptionsExtal Name FunctionMemory Map and Registers Synthesizer Control Register Syncr Register DescriptionsLolre MFD2 MFD1 MFD0 Locre Locen Disclk Fwkup STPMD1 STPMD0RFD MFDMFD20 Stpmd Synthesizer Status Register SynsrOSC PllmodeLocks Synsr Field DescriptionsFunctional Description Clock ModeSystem Clock Modes System Clock ModesSystem Clock Mode PLL Options Clock Operation During ResetSystem Clock Generation Clock Out and Clock In RelationshipsPLL Operation Phase and Frequency Detector PFDCharge Pump/Loop Filter Charge Pump Current and MFD in Normal Mode OperationVoltage Control Output VCO Multiplication Factor Divider MFDPLL Lock Detection PLL Loss of Lock Conditions PLL Loss of Lock ResetLoss of Clock Detection Loss of Clock ResetAlternate Clock Selection Loss of Clock Summary10. Stop Mode Operation Sheet 1 Loss of Clock in Stop ModeStop 10. Stop Mode Operation Sheet 2Expected PLL Action ‘LC NRM ‘LK 10. Stop Mode Operation Sheet 3NRM ‘LC ‘LK PLL 10. Stop Mode Operation Sheet 4Lose reference 10. Stop Mode Operation Sheet 5Clock ModesFunctional Description MCF5282 User’s Manual 10.1 68K/ColdFire Interrupt Architecture Overview Chapter Interrupt Controller Modules68K/ColdFire Interrupt Architecture Overview Interrupt Recognition Interrupt Controller Theory of OperationInterrupt Prioritization Interrupt Priority Within a LevelInterrupt Vector Determination Interrupt Controller Base Addresses Memory MapInterrupt Controller Memory Map Interrupt Controller Number Base AddressInterrupt Pending Registers IPRHn, IPRLn INT Maskall Interrupt Mask Register IMRHn, IMRLnIntmask Intfrc Interrupt Force Registers INTFRCHn, INTFRCLnIMRLn Field Descriptions IRQ Interrupt Request Level Register IRLRnInterrupt Control Register ICRnx, x = 1, 2 Interrupt Acknowledge Level and Priority Register IACKLPRn11. IACKLPRn Field Descriptions Level PRI13. Interrupt Source Assignment for INTC0 Interrupt Sources12. ICRnx Field Descriptions DTIM0 CAP/REF IIFDTIM1 CAP/REF DTIM2 CAP/REFPIT0 PIF Gptb TOFPIT1 PIF PIT2 PIF14. Interrupt Source Assignment for INTC1 Software and Level n Iack Registers SWIACKR, L1IACK-L7IACKVector Prioritization Between Interrupt ControllersLow-Power Wakeup Operation 10-18 Ipbus Low-Power Mode OperationIntroduction Interrupt/General-Purpose I/O Pin Descriptions Edge Port Module Operation in Low-power ModesLow-power Mode Eport Operation Mode Exit Edge Port Module Memory Map Bits AccessRegisters Eport Data Direction Register Epddr Eport Pin Assignment Register EpparEPPA7 EPPA5 EPPA4 EPPA3 EPPA2 EPPA1Epdd Field Descriptions Edge Port Interrupt Enable Register EpierEdge Port Data Register Epdr Epdr Field Descriptions Edge Port Pin Data Register EppdrEdge Port Flag Register Epfr EPF7-EPF1 Epfr Field Descriptions11-8 1lists signals used by the chip select module Chip Select Module SignalsChip Select Module Signals Signal DescriptionD3124 D2316 D158 D70 Byte Enables/Byte Write Enable Signal SettingsTransfer Size Port Size General Chip Select Operation Chip Select OperationAccesses by Matches in CSARs and DACRs External Boot Chip Select Operation12.3.1.1 8-, 16-, and 32-Bit Port Sizing BS2 BS1 BS0D1918 Boot Device/Data Port Size D1918 External Boot Chip Select ConfigurationChip Select Registers Chip Select RegistersChip Select Address Registers CSAR0-CSAR6 Chip Select Module RegistersCSARs, -2,specify the chip select base addresses 6describes Csarba7describes Csmr fields Chip Select Mask Registers CSMR0-CSMR6CSARn Field Description Csmr n Field Descriptions8describes CSCRn fields Chip Select Control Registers CSCR0-CSCR6SD,UC PS1 PS0 BEM Bstr BstwNo internal TA is asserted. Cycle is terminated externally CSCRn Field Descriptions12-10 Signal Name Description Clkout Edge Bus and Control SignalsColdFire Bus Signal Summary TIP Bus CharacteristicsData Transfer Operation Bus Cycle Execution Chip-Select Module Output Timing DiagramAccesses by Matches in CSCRs and DACRs State Cycle Data Transfer Cycle StatesBus Cycle States Read Cycle System MCF52823describes the six states of a basic write cycle Write cycle timing diagram is shown in FigureWrite Cycle Read Cycle with Fast Termination Fast Termination CyclesBurst Cycles Back-to-Back Bus CyclesA32 Longword Accesses Allowable Line Access PatternsLine Transfers Line Read Bus Cycles13shows timing when internal termination is used 16. Line Write Burst 2-1-1-1, Internal/External Termination Line Write Bus Cycles17shows a line burst write with one wait-state insertion Misaligned Operands19. Example of a Misaligned Longword Transfer 32-Bit Port 13-16 Chapter Signal Descriptions MCF5282 Block Diagram with Signal Interfaces Sdram Controller Signals MCF5282 Signal DescriptionSignal Name Abbreviation Function External Memory Interface Clock and Reset Signals Signal Name Abbreviation FunctionChip Configuration Module External Interrupt SignalsFlexCAN Signals Queued Serial Peripheral Interface Qspi Signals2C Signals Uart SignalsDMA Timer Signals General Purpose Timer SignalsAnalog-to-Digital Converter Qadc Signals Debug Support SignalsPower and Reference Signals 2lists signals in alphabetical order by abbreviated nameTest Signals Abbreviation Function MCF5282 Alphabetical Signal IndexVddpll TCK Chip Configuration/Mode Selection MCF5282 Signals and Pin Numbers Sorted by FunctionSecondary External Memory Interface and PortsSdram Controller Chip SelectsExternal Interrupts Port EthernetFlexCAN UARTs General Purpose TimersDebug and Jtag Test Port Control DMA TimersQueued Analog-to-Digital Converter Qadc Test Single-Chip ModePower Supplies Listing of signals that do not default to a Gpio function External Boot ModePin Reset States at Reset Single-Chip Mode Signal Reset Clock and Reset SignalsExternal Interface Module EIM Signals 14.2 MCF5282 External SignalsAddress Bus A230 Data Bus D310Transfer Error Acknowledge TEA Output Enable OETransfer Acknowledge TA Read/Write R/WTransfer In Progress TIP Transfer Start TSChip Selects CS60 Transfer Size EncodingSdram Controller Signals Chip Configuration Signals Clock and Reset SignalsEthernet Module Signals External Interrupt SignalsCollision Ecol Transmit Error EtxerReceive Clock Erxclk Receive Data Valid ErxdvQueued Serial Peripheral Interface Qspi Signals Uart Module Signals FlexCAN Signals14.2.9 I2C Signals General Purpose Timer Signals DMA Timer Signals Analog-to-Digital Converter Signals Debug Support Signals Development Serial Input/Test Data DSI/TDI Breakpoint/Test Mode Select BKPT/TMSDevelopment Serial Output/Test Data DSO/TDO Test Clock TclkDebug Data DDATA30 Test SignalsProcessor Status Outputs PST30 Test TestPower and Reference Signals 14-34 Definitions OverviewDACR0 Block Diagram and Major ComponentsDACR1 Scas Sras Scke SDRAMCS10 DramwSdram Controller Operation Sdram CommandsCommand Definition 2describes the behavior of Dram signals in synchronous mode Dram Controller SignalsMemory Map for Sdramc Registers Dram controller registers memory map is shown in TableDCR, shown in -2,controls refresh logic Dram Control Register DCR4describes DCR fields DCR Field Descriptions5describes DACRn fields Dram Address and Control Registers DACR0/DACR1DACRn Field Descriptions Bit15-7 Dram Controller Mask Registers DMR0/DMR1 Bit Associated Access Type Access Definition6describes DMRn fields DMRn Field DescriptionsAddress Multiplexing General Synchronous Operation GuidelinesGeneric Address Multiplexing Scheme Address Pin Row Address Column AddressMCF5282 Pins Row ColumnPins Row Column 15-12 Pins MCF5282 Burst Page ModeSdram Byte Strobe Connections Interfacing ExampleBurst Read Sdram Access Auto-Refresh Operation Burst Write Sdram AccessAuto-Refresh Operation Self-Refresh OperationSelf-Refresh Operation Initialization SequenceMode Register Settings Parameter Specification 25. Sdram Example SpecificationsSdram Example ClkoutDCR Initialization Sdram Interface ConfigurationDacr Initialization 26. Sdram Hardware ConnectionsDACRs should be programmed as shown in Figure Bits Name Setting Description28. Dacr Initialization Values Casl CBM Imrs29. DMR0 Initialization Values DMR Initialization30. Mode Register Initialization Mode Register Initialization31. Mode Register Mapping to MCF5282 A310 MCF5282 Pins Sdram Pins Mode Register InitializationInitialization Code Mode Register Initialization SequencePrecharge Sequence Refresh Sequence15-25 15-26 Chapter DMA Controller Module Channel 0 Channel 1 Channel 2 Channel DMA Module FeaturesDMA Request Control Dmareqc DMA DMA Transfer OverviewMemory Map for DMA Controller Module Registers DMA Controller Module Programming ModelDestination Address Registers DAR0-DAR3 Source Address Registers SAR0-SAR3SAR DARBCR Byte Count Registers BCR0-BCR33describes DCRn fields DMA Control Registers DCR0-DCR3DCRn Field Descriptions BWC Sinc Ssize Dinc Dsize StartEncoding BCR24BIT = BWCDSR n Field Descriptions DMA Status Registers DSR0-DSR34describes DSRn fields Transfer Requests Cycle-Steal and Continuous Modes DMA Controller Module Functional DescriptionBSY DoneDual-Address Transfers Data Transfer ModesProgramming the DMA Controller Module Channel Initialization and StartupChannel Prioritization Auto-Alignment Data TransferBandwidth Control Termination16-16 Chapter Fast Ethernet Controller FEC Interface Options Full and Half Duplex Operation17.2.2.1 10 Mbps and 100 Mbps MII Interface Primary operational modes are described in this sectionInternal Loopback 17.2.2.2 10 Mpbs 7-Wire Interface OperationAddress Recognition Options PAD FEC Top-Level Functional Diagram17-5 User Initialization Prior to Asserting Ecretheren Initialization SequenceHardware Controlled Initialization Ecretheren De-Assertion Effect on FECUser Initialization After Asserting Ecretheren Microcontroller InitializationFEC User Initialization Before Ecretheren Microcontroller InitializationWire Mode Configuration MII ModeSignal Description Emac pin Network Interface OptionsFEC Frame Transmission FEC Frame Reception Ethernet Address Recognition Ethernet Address Recognition-Receive Block Decisions Ethernet Address Recognitionq-Microcode Decisions Hash AlgorithmBit DA Bit Hash Hash Decimal Hex Value Destination Address to 6-Bit Hash17-15 Full Duplex Flow Control Pause Frame Field SpecificationInternal and External Loopback Inter-Packet Gap IPG TimeCollision Handling Transmission Errors Ethernet Error-Handling ProcedureHeartbeat Reception ErrorsDetailed Memory Map Control/Status Registers Top Level Module Memory MapModule Memory Map 10. FEC Register Memory MapMIB Block Counters Memory Map Mnemonic Description Offset 11. MIB Counters Memory MapFollowing sections describe each register in detail RegistersEthernet Interrupt Event Register EIR Babr Babt GRA TXF TXB RXF RXB MII Eberr Hberr Ieeetsqe17-25 Babr Babt GRA TXF TXB RXF RXB MII Interrupt Mask Register EimrReceive Descriptor Active Register Rdar Rdesactive Transmit Descriptor Active Register TdarXdesactive Etheren ResetEthernet Control Register ECR Data MII Management Frame Register Mmfr16. ECR Field Descriptions Bit Name Description 17. Mmfr Field DescriptionsDispreamble MII Speed Control Register MscrDispreamble Miispeed Mibdisable Mibdisable MibidleMIB Control Register Mibc 19. Programming Examples for MscrMaxfl Receive Control Register RCRFCE Bcrej Prom Miimode DRT Loop FCEGTS Transmit Control Register TCRTfcpause Fden Tfcpause Physical Address Low Register Palr22. TCR Field Descriptions PADDR1 Physical Address High Register PaurPADDR2 TypeDescriptor Individual Upper Address Register Iaur Opcode/Pause Duration Register OPD24. Paur Field Descriptions OpcodeIADDR1 Descriptor Individual Lower Address IalrBits Name Descriptions IADDR2Descriptor Group Lower Address Galr Descriptor Group Upper Address Gaur27. Ialr Field Descriptions GADDR1Xwmrk Fifo Transmit Fifo Watermark Register TfwrGADDR2 Rbound Fifo Receive Bound Register Frbr30. Tfwr Field Descriptions Rfstart Fifo Receive Start Register FrsrReceive Descriptor Ring Start Erdsr Xdesstart Transmit Buffer Descriptor Ring Start EtsdrRdesstart Rbufsize Receive Buffer Size Register Emrbr34. Etdsr Field Descriptions Driver/DMA Operation with Transmit BDs Buffer DescriptorsDriver/DMA Operation with Buffer Descriptors Driver/DMA Operation with Receive BDs RO1 RO2 Ethernet Receive Buffer Descriptor RxBDWord Location Field Name Description 36. Receive Buffer Descriptor Field DefinitionsRO1 ErdsrEthernet Transmit Buffer Descriptor TxBD TO1 TO1 TO2 ABC17-51 17-52 Low-power Mode Watchdog Operation Mode Exit Watchdog Module Operation in Low-power ModesRefer to -2for an overview of the watchdog memory map SignalsWatchdog timer module has no off-chip signals Watchdog Control Register WCR 16-bit WCR configures watchdog timer operationWatchdog Timer Module Memory Map WCR Field Descriptions Watchdog Modulus Register WMRWatchdog Count Register Wcntr Watchdog Service Register WSRWMR Field Descriptions WC9 WC8WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0 WS9 WS8Chapter Programmable Interrupt Timer Modules PIT0-PIT3 Low-power Mode PIT Operation Mode Exit PIT module has no off-chip signalsPIT Module Operation in Low-power Modes Ipsbar Offset Access For PITx Bits Address Programmable Interrupt Timer Modules Memory MapPRE3 PRE2 PRE1 PRE0 PIT Control and Status Register PcsrDoze Halted OVW PIE PIF RLD PREPIF PIT Modulus Register PMRThis subsection describes the PIT functional operation Set-and-Forget Timer OperationPIT Count Register Pcntr Timeout Specifications Free-Running Timer OperationSystem clock PIT Clock CounterInterrupt Operation Interrupt Request Flag Enable Bit Timeout4shows the interrupt request generated by the PIT PIT Interrupt RequestsChapter General Purpose Timer Modules Gpta and Gptb GPT Block Diagram Function Reset State Pull-up Name Register Bit Signal DescriptionGPTn20 PinGPTn3 Ipsbar Offset Bits AccessSYNCn GPT Modules Memory MapIOS GPT Input Capture/Output Compare Select Register GptiosGPT Output Compare 3 Mask Register GPTOC3M GPT Compare Force Register GpcforcGptios Field Descriptions FOCGPT Counter Register Gptcnt GPT Output Compare 3 Data Register GPTOC3DGPTOC3M Field Descriptions OC3DGptcnt Field Descriptions GPT System Control Register 1 GPTSCR1Gpten Tffca GptenGPT Control Register 1 GPTCTL1 GPT Toggle-On-Overflow Register GpttovTOV OM3 OL3 OM2GPT Control Register 2 GPTCTL2 GPT Interrupt Enable Register Gptie11. GPTCL1 Field Descriptions EDG3B EDG3A EDG2B EDG2A13. Gptie Field Descriptions GPT System Control Register 2 GPTSCR2GPT Flag Register 2 GPTFLG2 GPT Flag Register 1 GPTFLG1Pulse Accumulator Control Register Gptpactl GPT Channel Registers GPTCnCcnt PAE Pamod Pedge CLK Paovi PAIPaovf Paif Pulse Accumulator Flag Register GptpaflgPaclk Pacnt Pulse Accumulator Counter Register Gptpacnt19. Gptpaflg Field Descriptions GPT Port Data Direction Register Gptddr GPT Port Data Register Gptport22. Gptddr Field Descriptions PorttOutput Compare PrescalerInput Capture Pulse Accumulator Event Counter ModeGeneral-Purpose I/O Ports Gated Time Accumulation ModePulse Accumulator OM3 OL3Dir Function 23. GPT Settings and Pin FunctionsEDGx OMx OC3Mx Pin Data Driven Comments 24lists the interrupt requests generated by the timer ResetInterrupt Request Flag Enable Bit InterruptsGPT Channel Interrupts CnF Timer Overflow TOFPulse Accumulator Overflow Paovf Pulse Accumulator Input Paif20-23 20-24 Chapter DMA Timers DTIM0-DTIM3 Prescaler DMA Timer Programming ModelKey Features Output Mode Capture ModeDMA Timer Module Memory Map Reference CompareOrri FRR CLK RST DMA Timer Mode Registers DTMRn2describes the DTMRn fields DMA Timer Extended Mode Registers DTXMRnDTMRn Field Descriptions DTXMR3DTXMRn Field Descriptions DMA Timer Event Registers DTERn3describes the DTXMRn fields DMA Timer Capture Registers DTCRn DMA Timer Reference Registers DTRRn4describes the DTERn fields DTERn Field DescriptionsDMA Timer Counters DTCNn Using the DMA Timer ModulesCode Example T0LOOP Calculating Time-Out ValuesModule Description Chapter Queued Serial Peripheral Interface Qspi ModuleQspiclk Interface and SignalsQspi RAM Signal Name Hi-Z or Actively Driven Function Qspi Input and Output Signals and FunctionsOperation Internal Bus InterfaceQspi RAM Relative Address Register 0x00 Receive RAM0x01 0x0FTransmit RAM Command RAMBaud Rate Selection Qspiclk Frequency as Function of System Clock and Baud Rate Transfer DelaysSystem Clock 66.67 MHzTransfer Length Qspi Registers Programming Model4gives QMR field descriptions Qspi Mode Register QMRQMR Field Descriptions Value Bits per transferQspics Qmrcpol = Qspi Delay Register QdlyrQmrcpha = = Qdlyrqcd Qcrcont = = Qdlyrdtl QCD5gives Qdlyr field descriptions Qspi Wrap Register QWR6gives QWR field descriptions Qdlyr Field DescriptionsQIR Field Descriptions Qspi Interrupt Register QIR7describes QIR fields Addr Qspi Address Register QARQspi Data Register QDR QCR0-QCR15 Field Descriptions Command RAM Registers QCR0-QCR158gives QCR field descriptions QSPICS30 Programming ExampleQspiclk QS2 Qspidout QS3 Qspidin QS4 QS522-17 22-18 Ucts Urts Urxd Utxd UartSerial Module Overview Ipsbar Offset 3124 2316 158 Register DescriptionsUart Module Memory Map ERR Uart Mode Registers 1 UMR1n2describes UMR1n fields Parity Mode Parity Type PT=UMR1n Field Descriptions CTSUMR2 n Field Descriptions Uart Mode Register 2 UMR2n3describes UMR2n fields 4describes USRn fields Uart Status Registers USRnUMR2n Field Descriptions USRn Field DescriptionsRCS TCS Uart Clock Select Registers UCSRn5describes UCSRn fields UCSRn Field Descriptions Uart Command Registers UCRnRCS DtinUCR n Field Descriptions Bits Value Command DescriptionUCRn Field Descriptions Uart Receive Buffers URBnUart Transmit Buffers UTBn 7describes UIPCRn fields Uart Input Port Change Registers UIPCRnUipcr n Field Descriptions COS CTSUart Auxiliary Control Register UACRn UACRs, shown in -7,control the input enableUart Interrupt Status/Mask Registers UISRn/UIMRn 8describes UACRn fieldsUisr n/UIMR n Field Descriptions Uart Baud Rate Generator Registers UBG1n/UBG2n9describes UISRn and UIMRn fields Uart Input Port Register UIPn Uart Output Port Command Registers UOP1n/UOP0n10describes UIPn fields 11describes UOP1 and UOP0 fields11. UOP1/UOP0 Field Descriptions Ucts Uart Module Signal DefinitionsIRQ Programmable Divider 12. Uart Module SignalsTransmitter/Receiver Clock Source Calculating Baud Rates Following sections describe how to calculate baud ratesSystem Clock Baud Rates SysclkTransmitter Transmitter and Receiver Operating ModesTherefore UBG1n = 0x00 and UBG2n = 0xD6 External Clock23-21 Receiver 20. Transmitter Timing Diagram21shows receiver functional timing Fifo Stack23-24 Looping Modes Automatic Echo ModeLocal Loop-Back Mode Remote Loop-Back Mode Multidrop Mode25. Multidrop Mode Timing Diagram Programming Bus OperationRead Cycles Write CyclesSetting up the Uart to Request DMA Service Setting up the Uart to Generate Core InterruptsInterrupt and DMA Request Initialization 13. Uart InterruptsUart Module Initialization Sequence Register Setting15shows the Uart module initialization sequence 14. Uart DMA Requests26. Uart Mode Programming Flowchart Sheet 1 26. Uart Mode Programming Flowchart Sheet 2 26. Uart Mode Programming Flowchart Sheet 3 26. Uart Mode Programming Flowchart Sheet 4 26. Uart Mode Programming Flowchart Sheet 5 23-36 Chapter I2C Interface Interface FeaturesIfdr Acknowledge bit generation/detection Bus-busy detectionIadr SCL SDA24.4 I2C Protocol 24.3 I2C System ConfigurationRepeated Start Arbitration ProcedureHandshaking Clock SynchronizationClock Stretching SCL1 SCL22describes I2ADR fields 24.5.1 I2C Address Register I2ADRI2C Interface Memory Map I2ADR Field Descriptions3describes I2FDRIC 24.5.2 I2C Frequency Divider Register I2FDRI2FDR Field Descriptions Divider4describes I2CR fields 24.5.3 I2C Control Register I2CRI2CR Field Descriptions IEN Iien5describes I2SR fields 24.5.4 I2C Status Register I2SRI2SR Field Descriptions ICF Iaas IBB IAL SRW IIF24.5.5 I2C Data I/O Register I2DR 24.6 I2C Programming ExamplesPost-Transfer Software Response Generation of StartI2SR 24.6.4 Generation of StopGeneration of Repeated Start Slave ModeArbitration Lost IAAS=1 RXAK=SRW=1 Write24-16 Chapter FlexCAN Cantx Canrx RAM MB3 MB2 MB1 MB0FlexCAN Memory Map 25.1.2 External SignalsFlexCAN Memory Map Message Buffers Can SystemMessage Buffer Structure Typical can system is shown below in FigureCommon Fields for Extended and Standard Format Frames Message Buffer Codes for Transmit Buffers Common Extended/Standard Format FramesMessage Buffer Codes for Receive Buffers Fields for Extended Format Frames Message Buffer Memory MapFields for Standard Format Frames Extended Format FramesIdhigh Idlow Functional OverviewMessage Buffers Receive Process Transmit ProcessSelf-Received Frames Message Buffer HandlingReceive Message Buffer Deactivation Serial Message Buffers SMBsTransmit Message Buffer Deactivation Locking and Releasing Message Buffers Remote FramesTime Stamp Listen-Only ModeOverload Frames Bit Timing Configuring the FlexCAN Bit TimingExamples of System Clock/CAN Bit-Rate/S-Clock Freq Mhz Time-quanta/bit Value +FlexCAN Error Counters FlexCAN Initialization Sequence Special Operating Modes Debug ModeLow-Power Stop Mode for Power Saving Canmcr Interrupts Auto-Power Save ModeProgrammer’s Model Can Module Configuration Register Canmcr8describes the Canmcr fields Stop FRZ Halt Notrdy Wakemsk Softrst FrzackStop Canmcr Field Descriptions9describes the CANCTRL0 fields FlexCAN Control Register 0 CANCTRL0Transmit Pin Configuration 10. Transmit Pin ConfigurationFlexCAN Control Register 1 CANCTRL1 11describes the CANCTRL1 fields12describes the Presdiv fields Prescaler Divide Register Presdiv11. CANCTRL1 Field Descriptions Samp13describes the CANCTRL2 fields FlexCAN Control Register 2 CANCTRL212. Presdiv Field Descriptions 13. CANCTRL2 Field Descriptions14describes the Timer fields Free Running Timer Timer14. Timer Field Descriptions Rx Mask Registers12. Rx Mask Registers RXGMASK, RX14MASK, and RX15MASK Receive Mask Registers RXGMASK, RX14MASK, RX15MASK16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions FlexCAN Error and Status Register Estat17describes the Estat fields Biterr 17. Estat Field Descriptions18describes the Imask fields Interrupt Mask Register ImaskBUF15M BUF14M BUF13M BUF10M BUF9M BUF8M19describes the Iflag fields Interrupt Flag Register Iflag18. Imask Field Descriptions 19. Iflag Field DescriptionsFlexCAN Transmit Error Counter Txectr FlexCAN Receive Error Counter Rxectr20describes the Rxectr fields 21describes the Txectr fieldsChapter General Purpose I/O Module MCF5282 Ports Module Block Diagram Sdram control Bit DMA timers Uart transmit/receive FeaturesOverview Modes of OperationMCF5282 Ports External Signals External Signal DescriptionSDA ErxerSCL UCTS0Memory Map/Register Definition 31-24 23-16 15-8 AccessRegister Overview MCF5282 Ports Module Memory MapDdreh Ddrel Ddrb DdrcClra Clrb Clrc Clrd Clre Clrf Clrg ClrhPort Output Data Registers 8-bit Port Output Data Registers PORTnPORTn bits are described in Table Port Data Direction Registers DDRnPORTn 8-bit, 7-bit, 6-bit, and 4-bit Field Descriptions Register Bits Name DescriptionPort Data Direction Register 7-bit 10. Port Pin Data/Set Data Registers 8-bit Port Pin Data/Set Data Registers PORTnP/SETnPORTnP/SETn bits are described in Table Port Clear Output Data Registers CLRnPORTnP/SETn 8-bit, 6-bit, and 4-bit Field Descriptions PORTUAP/SETUACLRn 8-bit,7-bit, 6-bit, and 4-bit Field Descriptions CLRn register bits are described in TablePort Size Pbpa Reset Pcdpa Reset Reset Values for Pbcdpar BitsExternal Boot Port B/C/D Pin Assignment Register PbcdparPEPA3 Port E Pin Assignment Register PeparPepar Field Descriptions Single chip mode 10. Reset Values for Pepar Bits and Fields11. Pfpar Field Descriptions Port F Pin Assignment Register PfparPfpar controls the pin function of port F75 12. Pjpar Field Descriptions Port J Pin Assignment Register PjparPjpar controls the pin function of port J Port AS Pin Assignment Register Paspar Port SD Pin Assignment Register PsdparPsdpar controls the pin function of port SD Paspar controls the pin function of port AS14. Paspar Field Descriptions Port EH/EL Pin Assignment Register PehlparPqspar controls the pin function of port QS Port QS Pin Assignment Register Pqspar15. Pehlpar Field Descriptions ECOL, ERXCLK, ERXDV, ERXD0, EcrsPTCPA3 PTCPA2 PTCPA1 PTCPA0 Port TC Pin Assignment Register PtcparPtcpar controls the pin function of port TC PTDPA3 PTDPA2 PTDPA1 PTDPA0 Port TD Pin Assignment Register PtdparPtdpar controls the pin function of port TD Puapar controls the pin function of port UA Port UA Pin Assignment Register PuaparClkout Input PIN Register PIN Data Port Digital I/O TimingClkout Output Data Register Output PIN Initialization/Application InformationChapter Queued Analog-to-Digital Converter Qadc Qadc Block Diagram Modes of Operation Debug ModePort QA Analog Input Signals Port QA Signal FunctionsPort QB Analog Input Signals Port QB Signal FunctionsPort QA Digital Input/Output Signals Multiplexed Address Output Signals External Trigger Input SignalsMultiplexed Analog Input Signals Port QB Digital I/O SignalsDedicated Analog Supply Signals Voltage Reference SignalsDedicated Digital I/O Port Supply Signal Multiplexed Analog Input ChannelsQadc Memory Map Qadc Module Configuration Register QadcmcrThis subsection describes the Qadc registers Port Data Registers Portqa and Portqb Qadc Test Register QadctestANZ ANY ANX ANW Port QA and QB Data Direction Register Ddrqa and DdrqbThis subsection describes the Qadc control registers Control RegistersQadc Control Register 0 QACR0 QPR6 Qadc Control Register 0 QACR0 QACR0 Field DescriptionsDivisor Prescaler fSYS Divide-by ValuesQPR60 CIE1 Qadc Control Register 1 QACR1CIE1 PIE1 SSE1 Queue 1 Operating Modes Operating ModeQadc Control Register 2 QACR2 Resume CIE2 PIE2 SSE2Queue 2 Operating Modes QACR2 Field DescriptionsCIE2 BQ2Qadc Status Register 0 QASR0 Status RegistersThis subsection describes the Qadc status registers MQ2128 Operating Modes27-20 Queued Analog-to-Digital Converter Qadc 27-21 QS7 QS6 CWP5 CWP4 CWP3 CWP2 CWP1 CWP0 CF1 PF1 CF2QS9 QS8 10. QASR0 Field Descriptions Scan Mode Queue Operation PF Asserts?11. CCW Pause Bit Response CWPQueue 1/Queue 2 States 12. Queue Status12. Queue Status Transition Qadc Status Register 1 QASR1 Conversion Command Word Table CCWIST1 IST0 BYPPort Signal Name Non-Multiplexed Input Signals Channel Number15. Input Sample Times IST10 Input Sample TimesMultiplexed Input Signals Channel Number 17. Multiplexed Channel Assignments and Signal DesignationsResult Registers Right-Justified Unsigned Result Register RjurrLeft-Justified Unsigned Result Register Ljurr Left-Justified Signed Result Register Ljsrr18. Rjurr Field Descriptions ResultExternal Multiplexing 27.7 Functional DescriptionResult Coherency External Multiplexing Operation 18. External Multiplexing Configuration Module Version Options Analog SubsystemAnalog-to-Digital Converter Operation 21. Analog Input ChannelsConversion Cycle Times 19. Qadc Analog Subsystem Block DiagramSample Buffer Channel Decode and MultiplexerComparator Digital Control SubsystemBias Successive Approximation Register SARQueue Priority Queue Priority Timing Examples22. Qadc Queue Operation with Pause 22. Trigger Events Queue Priority Schemes23. Status Bits Events23. CCW Priority Situation 24. CCW Priority Situation 26. CCW Priority Situation 28. CCW Priority Situation 30. CCW Priority Situation 32. CCW Priority Situation 34. CCW Freeze Situation 38. CCW Freeze Situation Boundary Conditions Reserved Mode Disabled ModeScan Modes Single-Scan ModesSoftware-Initiated Single-Scan Mode Externally Gated Single-Scan Mode Externally Triggered Single-Scan ModeInterval Timer Single-Scan Mode Continuous-Scan Modes Software-Initiated Continuous-Scan Mode Externally Gated Continuous-Scan Mode Externally Triggered Continuous-Scan ModeQadc Clock Qclk Generation Periodic Timer Continuous-Scan Mode42. Qadc Clock Subsystem Functions Periodic/Interval Timer43illustrates the operation of the queue structure Conversion Command Word Table43. Qadc Conversion Queue Operation Queued Analog-to-Digital Converter Qadc 27-61 Result Word Table Signal Connection ConsiderationsAnalog Power Signals Analog Reference SignalsConversion Timing Schemes 45. Errors Resulting from Clipping46. External Positive Edge Trigger Mode Timing with Pause 47. Gated Mode, Single Scan Timing 48. Gated Mode, Continuous Scan Timing Analog Supply Filtering and Grounding49. Star-Ground at the Point of Power Supply Origin Accommodating Positive/Negative Stress Conditions 50. Input Signal Subjected to Negative StressIinjp IinjnAnalog Input Considerations 52. External Multiplexing of Analog Signal Sources 53. Electrical Model of an A/D Input Signal Analog Input PinsSource Resistance RF + Rsrc 100 Ω 10 kΩ 100 kΩ Settling Time for the External Circuit24. External Circuit Settling Time to 1/2 LSB Interrupt Operation Error Resulting from Leakage25. Error Resulting from Input Leakage IOff 26. Qadc Status Flags and Interrupt Sources Interrupt SourcesQueue Queue Activity Status Interrupt Flag PF1 PIE1Chapter Reset Controller Module Rsti Reset Controller Signal PropertiesRsto Name Direction InputReset Controller Memory Map Reset Control Register RCRLvdf Reset Status Register RSRLvdie Soft WDR PORWDR RSR Field DescriptionsPower-On Reset Reset SourcesReset Source Summary Source TypeWatchdog Timer Reset External ResetLoss-of-Clock Reset Loss-of-Lock ResetReset Control Flow Reset Control Flow Synchronous Reset Requests Concurrent ResetsInternal Reset Request Power-On Reset/Low-Voltage Detect ResetReset Status Flags 28-12 Processor/Debug Module Interface Debug module is shown in FigureDebug Module Signals Signal DescriptionPST30 Definition Hex Real-Time Trace SupportProcessor Status Encoding PST30 Definition Hex Binary Begin Execution of Taken Branch PST =Ddata Clkout PSTAblr AatrAbhr CSRBDM/Breakpoint Registers Revision a Shared Debug ResourcesRev. a Shared BDM/Breakpoint Hardware DRc4-0 Register Name Abbreviation Initial State5describes Aatr fields Address Attribute Trigger Register AatrAatr Field Descriptions TMMAddress Breakpoint Registers ABLR, Abhr Address Breakpoint Registers ABLR, Abhr6describes Ablr fields Configuration/Status Register CSR7describes Abhr fields Ablr Field DescriptionCSR Field Descriptions 8describes CSR fieldsIPI Data Breakpoint/Mask Registers DBR, Dbmr10describes Dbmr fields Program Counter Breakpoint/Mask Registers PBR, Pbmr9describes DBR fields 12describes PBR fields Trigger Definition Register TDR13describes Pbmr fields 12. PBR Field Descriptions14. TDR Field Descriptions 14describes TDR fieldsCPU Halt Background Debug Mode BDMEdum Eduu29-17 DSO BDM Serial InterfaceClkout Dsclk DSI Transmit Packet Format Receive Packet Format15describes receive BDM packet fields 16describes transmit BDM packet fieldsSection Command BDM Command Set17. BDM Command Summary 18describes BDM fields ColdFire BDM Command FormatExtension Words as Required 18. BDM Field Descriptions16. Command Sequence Diagram Command Sequence DiagramsRead A/D Register RAREG/RDREG Command Set DescriptionsCommand Sequence Read Memory Location Read Write A/D Register WAREG/WDREG22. Read Command Sequence 21. Read Command/Result FormatsWrite Memory Location Write 23. Write Command FormatDump Memory Block Dump Set is returned if a bus error occursOperands are sent as 16 and 32 bits, respectively 25. Dump Command/Result Formats Fill Memory Block Fill 26. Dump Command Sequence28. Fill Command Sequence 27. Fill Command FormatNo Operation NOP Resume Execution GO19. Control Register Map Read Control Register RcregRc encoding BDM Accesses of the Emac Registers BDM Accesses of the Stack Pointer Registers A7 SSP, USPWrite Control Register Wcreg 35. Wcreg Command/Result Formats20shows the definition of DRc encoding Read Debug Module Register RdmregDRc40 Debug Register Definition Mnemonic Initial State Write Debug Module Register Wdmreg20. Definition of DRc Encoding-Read Theory of Operation Real-Time Debug Support21. DDATA30/CSRBSTAT Breakpoint Response Breakpoint StatusEmulator Mode Concurrent BDM and Processor Operation Processor Status, Ddata Definition 22. PST/DDATA Specification for User-Mode InstructionsUser Instruction Set Instruction Operand Syntax29-41 29-42 23. PST/DDATA Specification for MAC Instructions Supervisor Instruction Set 24. PST/DDATA Specification for Supervisor-Mode InstructionsMotorola-Recommended BDM Pinout Reset DSIGND Dsclk GND PST3 PST2 PST1 PST0 DDATA3 DDATA2 DDATA1 DDATA029-46 Chapter Chip Configuration Module CCM Chip Configuration Module Block Diagram Single-Chip Mode30.4.3 D2624, 21, 1916 Reset Configuration Override Signal Descriptions1provides an overview of the CCM signals RconConfiguration Read/Write Access Write-Once Bits Read/Write AccessibilityFollowing subsection describes the CCM registers Chip Configuration Register CCRSzen BMTBootps Reset Configuration Register RconRcsc Rpllsel Rpllref RcscBootps Port Size Configuration Rcsc Chip Select ConfigurationChip Select Configuration Boot Port SizePIN PRN Reset ConfigurationChip Identification Register CIR 10. Configuration During Reset Reset Configuration Pin States During ResetD2524 Chip Mode SelectionClock Mode Output Pad Strength Configuration Boot Device SelectionClock Mode Selection 11. Chip Configuration Mode SelectionCCM does not generate interrupt requests Chip Select Configuration13. Clock Mode Selection Chapter Ieee 1149.1 Test Access Port Jtag Jtag Block Diagram 31.3.1 Detailed Signal Description External Signal DescriptionJtagen Jtag Enable Pin Function SelectedTRST/DSCLK Test Reset / Development Serial Clock 31.3.1.3 TMS/BKPT Test Mode Select / BreakpointSignal State to the Disable Module Tclk Test Clock InputMemory Map Memory Map/Register DefinitionInstruction Shift Register IR Idcode RegisterJtagcfmclkdiv Register Bypass RegisterTestctrl Register Boundary Scan RegisterTAP Controller Jtag Module5describes public and private instructions Jtag InstructionsJtag Instructions Instruction IR30 Instruction SummarySAMPLE/PRELOAD Instruction External Test Instruction ExtestIdcode Instruction Lockoutrecovery Instruction Enabletestctrl InstructionTestleakage Instruction Highz InstructionRestrictions Initialization/Application InformationClamp Instruction Bypass InstructionNonscan Chain Operation Chapter Mechanical Data MCF5282 Pinout 256 Mapbga PinoutSecondary Tertiary MCF5282 Signal Description by Pin NumberMapbga Pin Pin Functions PG3 PG4PG2 PF4GPTB0 PUA1 VDDGPTA0 PQA3 ETRIG1 VRH VDD Vssa VSSPUA3 VSS Xtal Jtagen PQA0 MA0 VDD VddaGPTB2 PQS5Orderable Part Numbers Motorola Part Description Speed TemperatureOrdering Information 32-8 Absolute Maximum Ratings1 Rating Symbol Value UnitMaximum Ratings HBM Rating SymbolThermal Characteristics Thermal CharacteristicsCharacteristic Symbol Value Unit 2lists thermal resistance valuesDC Electrical Specifications1 DC Electrical SpecificationsCharacteristic Symbol Min Max Unit Solving equations 1 and 2 for K givesWait Doze Stop PLL Electrical Specifications Phase Lock Loop Electrical SpecificationsQadc Electrical Specifications Operating Qadc Electrical CharacteristicsParameter Symbol Min Max Unit Qadc Absolute Maximum RatingsIOH = TBD Parameter Symbol MinQadc Conversion Specifications Operating Flash Memory CharacteristicsSgfm Flash Program and Erase Characteristics Num Parameter Symbol Min Max Unit10. Processor Bus Input Timing Specifications External Interface Timing CharacteristicsSgfm Flash Module Life Characteristics 11. External Bus Output Timing Specifications Processor Bus Output Timing SpecificationsName Characteristic Symbol Min Max Unit Control Outputs Timings listed in -10are shown in FigureData Outputs Read/Write Internally Terminated Timing Read Bus Cycle Terminated by TA Read Bus Cycle Terminated by TEA Sras Scas Dramw Symbol Min Max UnitSras SCAS1 Dramw 33.9 General Purpose I/O Timing13. Gpio Timing1 14. Reset and Configuration Override Timing Reset and Configuration Override Timing15. I2C Input Timing Specifications between SCL and SDA 33.11 I2C Input/Output Timing SpecificationsNum Characteristic Min Max Units Clkout Rsti Rsto16. I2C Output Timing Specifications between SCL and SDA Fast Ethernet AC Timing SpecificationsMII Transmit Signal Timing ETXD30, ETXEN, ETXER, Etxclk MII Receive Signal Timing ERXD30, ERXDV, ERXER, and Erxclk17. MII Receive Signal Timing Num Characteristic Min Max Unit19lists MII asynchronous inputs signal timing MII Async Inputs Signal Timing Ecrs and Ecol18. MII Transmit Signal Timing 19. MII Async Inputs Signal Timing20. MII Serial Management Channel Timing MII Serial Management Channel Timing Emdio and EmdcQspi Electrical Specifications DMA Timer Module AC Timing Specifications21lists timer module AC timings 22lists Qspi timings23. Jtag and Boundary Scan Timing Jtag and Boundary Scan Timing16. Boundary Scan Jtag Timing 17. Test Access Port TimingClkout VIL Debug AC Timing Specifications24. Debug AC Timing Specification 20. Real-Time Trace AC Timing 20shows real-time trace timing for the values in TableAddress Name Mnemonic Size Table A-1. CPU Space Register Memory MapACR0 ACR1Address Module Size Table A-2. Module Memory Map OverviewI2C QadcAddress Name Mnemonic Size SCM Registers Table A-3. Register Memory MapSdramc Registers Chip Select RegistersDMA Registers Uart Registers UIMR1 UISR1UBG21 UIP01Qspi Registers DMA Timer RegistersI2C Registers Interrupt Controller Ipsbar + 0xC56 IPRH1 SWACKR0IPRL1 IMRH1FEC Registers Global Interrupt Acknowledge Cycle RegistersGpio Registers Portqs PortasPortsd PorttcSeta Ipsbar + PortapPortbp Setb Ipsbar +Clrf ClraClrg ClrasEdge Port Registers Clock Module RegistersWatchdog Timer Registers Qadc Registers General Purpose Timer a RegistersGeneral Purpose Timer B Registers FlexCAN Registers Flash Registers MCF5282 User’s Manual Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13 Index-14 Index-15 Index-16

Table iii. Revision History

Revision

Date of

Substantive Changes

Number

Release

Figure 8-2/8-5

Figure 9-2/9-4

Figure 12-4/12-8

FRSR.”