Motorola MCF5282, MCF5281 user manual Data Transfer, Auto-Alignment

DMA Controller Module Functional Description

BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. DSRn[DONE] must be cleared for channel startup.

As soon as the channel has been initialized, it is started by writing a one to DCRn[START] or asserting DREQn, depending on the status of DCRn[EEXT]. Programming the channel for internal requests causes the channel to request the bus and start transferring data immediately. If the channel is programmed for external request, DREQn must be asserted before the channel requests the bus.

Changes to DCRn are effective immediately while the channel is active. To avoid problems with changing a DMA channel setup, write a one to DSRn[DONE] to stop the DMA channel.

16.5.4 Data Transfer

This section describes auto-alignment and bandwidth control for DMA transfers.

16.5.4.1Auto-Alignment

Auto-alignment allows block transfers to occur at the optimal size based on the address, byte count, and programmed size. To use this feature, DCRn[AA] must be set. The source is auto-aligned if DCRn[SSIZE] indicates a transfer size larger than DCRn[DSIZE]. Source alignment takes precedence over the destination when the source and destination sizes are equal. Otherwise, the destination is auto-aligned. The address register chosen for alignment increments regardless of the increment value. Configuration error checking is performed on registers not chosen for alignment.

If BCRn is greater than 16, the address determines transfer size. Bytes, words, or longwords are transferred until the address is aligned to the programmed size boundary, at which time accesses begin using the programmed size.

If BCRn is less than 16 at the start of a transfer, the number of bytes remaining dictates transfer size. For example, AA = 1, SARn = 0x0001, BCRn = 0x00F0, SSIZE = 00 (longword), and DSIZE = 01 (byte). Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on destination registers. The access sequence is as follows:

1.Read byte from 0x0001—write 1 byte, increment SARn.

2.Read word from 0x0002—write 2 bytes, increment SARn.

3.Read longword from 0x0004—write 4 bytes, increment SARn.

4.Repeat longwords until SARn = 0x00F0.

5.Read byte from 0x00F0—write byte, increment SARn.

If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size.

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