8 ELECTRICAL CHARACTERISTICS
EDO DRAM random access cycle (basic cycle)
| Data transfer #1 |
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| Next data transfer | |
RAS1 | CAS1 | PRE1(precharge) | RAS1' | CAS1' | |
BCLK |
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tAD | tAD | tAD |
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A[23:0] |
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| tRASD1 |
| tRASD2 |
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| tRASW |
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#RAS |
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| tCASD1 | tCASD2 |
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#HCAS/ |
| tCASW |
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#LCAS |
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| tRDD1 |
| tRDD3 |
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| tRDW2 |
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#RD |
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| tRACE | tCACE |
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| tACCE |
| ∗ 1 |
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| tRDS2 | tRDH |
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D[15:0] |
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| tWRD1 |
| tWRD3 |
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| tWRW2 |
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#WE |
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| tWDD1 | tWDD2 |
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D[15:0] |
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∗1 tRDH is measured with respect to the first signal change (negation) of either the #RD or the #RASx signals.
EDO DRAM page access cycle
| Data transfer #1 | Data transfer #2 |
| Next data transfer |
RAS1 | CAS1 | CAS2 | PRE1(precharge) | RAS1' |
BCLK |
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tAD | tAD | tAD |
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A[23:0] |
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| tRASD1 |
| tRASD2 |
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| tRASW |
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#RAS |
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| tCASD1 | tCASD2 |
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#HCAS/ |
| tCASW |
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#LCAS |
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| tRDD1 |
| tRDD3 |
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| tRDW2 |
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#RD |
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| tACCE |
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| tRACE | tCACE | tRDS tRDH ∗ 1 |
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| tRDS tRDH |
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| tACCE |
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D[15:0] |
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| tWRD1 |
| tWRD3 |
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| tWRW2 |
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#WE |
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| tWDD1 | tWDD2 | tWDD2 |
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D[15:0] |
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∗1 tRDH is measured with respect to the first signal change from among the #RD (negation), #RASx (negation) and #CAS (fall) signals.
S1C33L03 PRODUCT PART | EPSON |