VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
1.The device acting as the external bus master prompts the S1C33 to be prepared to release the bus by means of an interrupt or some other means.
2.When the S1C33 becomes ready to release the bus, it sets SDRSRF (D5/0x39FFC1) to "1" to place the SDRAM in
3.After the SDRAM is placed in
4.Simultaneously with 3, the external device pulls the SDCKE signal low to ensure that the SDRAM will not be taken out of
5.In response to the bus request, the S1C33 releases the external bus. The external bus, including the SDRAM interface pins, goes to a
6.The external bus master takes over control of the SDRAM. If SDRCLK (D3/0x39FFC1) = "1", a clock for the SDRAM is output from the BCLK pin. Therefore, the external bus master must control the SDRAM synchronously with that clock. If SDRCLK = "0", BCLK also goes to a
Note: If the SDRAM is not accessed after the bus is released, pull the SDRAM’s CKE pin down to low to
keep the
EPSON | S1C33L03 FUNCTION PART |