5
The same clock source must be used for the prescaler operating clock and the CPU operating clock. Therefore, when operating the CPU in
Function | Control bit | "1" | "0" | Default |
Prescaler operating clock | PSCDT0 (D0)/Prescaler clock select register(0x40181) | OSC1 | OSC3/ | OSC3/ |
switch over |
|
| PLL | PLL |
The LCD controller provides the power save mode on its own. Since the power save mode can be controlled by software, set the mode when turning the LCD display off.
Function | Control bit | "11" | "00" | Default |
Power save mode | LPSAVE[1:0] D([1:0])/LCDC mode register 2 | Normal | Power | Power |
| (0x39FFE3) | operation | save mode | save mode |
Note: The power save mode switches the LCD panel power control signal (LCDPWR) to the inactive state. This may cause damage of the LCD panel if the clock supply to the LCD controller is stopped at the same time.
Therefore, do not stop the clock supply for 1 frame cycles or more after setting the LCD controller to power save mode.
S1C33L03 PRODUCT PART | EPSON |