Epson S1C33L03 508

CPU–SDRAM clock ratio is set to 1 : 1. The SDRAM clock and the CPU system clock will be the same.

CPU–SDRAM clock ratio is set to 2 : 1. The SDRAM clock frequency becomes half of the CPU system clock.

VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE

SDRAM Operation

Synchronous Clock

The SDRAM controller uses the BCLK pin as it outputs the SDRAM clock.

To CPU

PLLS[1:0] pins

#X2SPD pin

CLG

Bus clock

CLKDT[1:0]

CLKCHG

BCU

High-speed (OSC3)

OSC3_CLK

BCLKSEL[1:0]

oscillation circuit

1/1–1/8

CPU_CLK

BCU_CLK

SDRENA

PLL_CLK

1/1 or 1/2

CPU_CLK

PLL

OSC3_CLK

PLL_CLK

BCLK pin

SDRAMC

Low-speed (OSC1)

1/1 or 1/2

SD_CLK

oscillation circuit

Refresh

counter

Figure 2.8 SDRAM Clock System

Normally output from the BCLK pin is a clock selected with the BCU’s BCLKSEL[1:0] (D[1:0])/BCLK select register (0x4813A) (which is, by default, the CPU clock). Before SDRAM can be used, the SDRAM clock can be enabled for output by writing "1" to the SDRENA (D7)/SDRAM control register (0x39FFC1).

The SDRAM clock has its frequency determined by how the #X2SPD pin is set, as does the BCU operating clock (BCU_CLK).

#X2SPD = "1":

#X2SPD = "0":

While the SDRAM is self-refreshed, the SDRAM clock output can be turned off in order to reduce the chip’s current consumption. To set this feature, use the SDRCLK (D3)/SDRAM control register (0x39FFC1). SDRCLK = "1": The BCLK pin always outputs SDRAM clock (default).

SDRCLK = "0": The BCLK pin is fixed low while the SDRAM is self-refreshed. It is placed in the high- impedance state while control of the bus is released.

When #X2SPD = "1"

#SDCEx OSC3 (CPU_CLK) BCLK (BCU_CLK)

BCLK (SD_CLK when SDRCLK = "1")

BCLK (SD_CLK when SDRCLK = "0")

SDCKE

Self refresh