VII LCD CONTROLLER BLOCK: LCD CONTROLLER
EDMAEN: Enable external DMA (D3) / LCDC system control register (0x39FFFD)
Enables/disables DMA requests from external devices while the LCD controller is in use.
Write "1": Enabled
Write "0": Disabled
Read: Valid
Setting EDMAEN to "1" enables DMA requests from other external devices even while the LCD controller is in use. During a DMA transfer by one of these external devices, the LCD controller cannot access the display memory and therefore cannot update the display. Setting EDMAEN to "0" disables DMA requests from external devices only while the LCD controller is in use (LCDCEN = "1").
At initial reset, EDMAEN is set to "0" (disabled).
BREQEN: Enable external bus request (D2) / LCDC system control register (0x39FFFD)
Enables/disables bus release requests from external devices while the LCD controller is in use.
Write "1": Enabled
Write "0": Disabled
Read: Valid
Setting BREQEN to "1" enables bus release requests from other external devices even while the LCD controller is in use. While the bus is being used by one of these external devices, the LCD controller cannot access the display memory and therefore cannot update the display. Setting BREQEN to "0" disables bus release requests from external devices only while the LCD controller is in use (LCDCEN = "1").
At initial reset, BREQEN is set to "0" (disabled).
LCDCST: A0/BSL select (D1) / LCDC system control register (0x39FFFD)
Selects the display memory (SRAM) interface method.
Write "1": BSL
Write "0": A0
Read: Valid
This setting is only effective when SRAM is used for the display memory.
Set the same value here as set in SBUSST (D3/0x4812E) for the BCU. When SDRAM is used, the settings of this register are ignored.
At initial reset, LCDCST is set to "0" (A0).
LCDCEC: Big/Little endian select (D0) / LCDC system control register (0x39FFFD)
Selects the LCD controller’s access format (little or big endian).
Write "1": Big endian
Write "0": Little endian
Read: Valid
Setting LCDCEC to "1" causes the LCD controller to be accessed in big endian format, and setting LCDCEC to "0" causes it to be accessed in little endian format. Set the same value here as set in A6EC (D1/0x48132) for area 6. At initial reset, LCDCEC is set to "0" (little endian).
LCDC
S1C33L03 FUNCTION PART | EPSON |