V DMA BLOCK: HSDMA
RHDM0: Ch.0 IDMA request (D4) / Port input
RHDM1: Ch.1 IDMA request (D5) / Port input
Specify whether IDMA need to be invoked when an interrupt factor occurs.
When using the
Write "1": IDMA request
Write "0": Not changed
Read: Valid
When using the read/write method
Write "1": IDMA request
Write "0": Interrupt request
Read: Valid
RHDM0 and RHDM1 are the IDMA request bits for HSDMA channels 0 and 1, respectively. If the bit is set to "1", IDMA is invoked when an interrupt factor occurs, thus performing a programmed data transfer. If the register is set to "0", regular interrupt processing is performed without ever invoking IDMA.
For details on IDMA, refer to "IDMA (Intelligent DMA)". At initial reset, RHDMx is set to "0" (interrupt request).
DEHDM0: Ch.0 IDMA enable (D4) / Port input
DEHDM1: Ch.1 IDMA enable (D5) / Port input
Enables IDMA transfer by means of an interrupt factor.
When using the
Write "1": IDMA enabled
Write "0": Not changed
Read: Valid
When using the read/write method
Write "1": IDMA enabled
Write "0": IDMA disabled
Read: Valid
DEHDM0 and DEHDM1 are the IDMA enable bits for HSDMA channels 0 and 1, respectively. If DEHDMx is set to "1", the IDMA request by the interrupt factor is enabled. If the bit is set to "0", the IDMA request is disabled.
At initial reset, DEHDMx is set to "0" (IDMA disabled).
HSDMA
S1C33L03 FUNCTION PART | EPSON |