III PERIPHERAL BLOCK: INPUT/OUTPUT PORTS
Conditions for port
Each port input interrupt can be generated by the edge or level of the input signal. The SEPTx bit of the edge/level select register (0x402C9) is used for this selection. When SEPTx is set to "1", the FPTx interrupt will be generated at the signal edge. When SEPTx is set to "0", the FPTx interrupt will be generated by the input signal level.
Furthermore, the signal polarity can be selected using the SPPTx bit of the input porarity select register (0x402C8).
With these registers, the port input interrupt condition is decided as shown in Table 9.6.
Table 9.6 | Port Input Interrupt Condition | ||
SEPTx |
| SPPTx | FPTx interrupt condition |
1 |
| 1 | Rising edge |
1 |
| 0 | Falling edge |
0 |
| 1 | High level |
0 |
| 0 | Low level |
When the input signal goes to the selected status, the interrupt factor flag FP is set to "1" and, if other interrupt conditions set by the interrupt controller are met, an interrupt is generated.
I/O
S1C33L03 FUNCTION PART | EPSON |