III PERIPHERAL BLOCK: SERIAL INTERFACE
RXD07–RXD00: Ch.0 receive data (D[7:0]) / Serial I/F Ch.0 receive data register (0x401E1)
RXD17–RXD10: Ch.1 receive data (D[7:0]) / Serial I/F Ch.1 receive data register (0x401E6)
RXD27–RXD20: Ch.2 receive data (D[7:0]) / Serial I/F Ch.2 receive data register (0x401F1)
RXD37–RXD30: Ch.3 receive data (D[7:0]) / Serial I/F Ch.3 receive data register (0x401F6)
Stores received data.
When a receive operation is completed and the data received in the shift register is transferred to this register (receive buffer), RDBFx is set to "1" (receive buffer full). At the same time, a receive-buffer full interrupt factor is generated. Thereafter, the data can be read out at any time before a receive operation for the next data is completed. If the next data receive operation is completed before this register is read out, the data in it is overwritten with the newly received data, causing an overrun error to occur.
In the 7-bit asynchronous mode, "0" is stored in RXDx7.
The serial data input from the SINx pin is converted into parallel data beginning with the LSB, with the high-level signals changed to "1"s and the low-level signals changed to "0"s. The resulting data is stored in this buffer.
This register is a read-only register, so no data can be written to it. At initial reset, the content of RXDx becomes indeterminate.
TEND0: Ch.0 transmit-completion flag (D5) / Serial I/F Ch.0 status register (0x401E2)
TEND1: Ch.1 transmit-completion flag (D5) / Serial I/F Ch.1 status register (0x401E7)
TEND2: Ch.2 transmit-completion flag (D5) / Serial I/F Ch.2 status register (0x401F2)
TEND3: Ch.3 transmit-completion flag (D5) / Serial I/F Ch.3 status register (0x401F7)
Indicates the transmission status.
Read "1": During transmitting
Read "0": End of transmission
Write: Invalid
TENDx goes "1" when data is being transmitted and goes "0" when the transmission has completed. When data is transmitted successively in clock-synchronized master mode or asynchronous mode, TENDx maintains "1" until all data is transmitted (see Figure 8.4 and Figure 8.12). In clock-synchronized slave mode, TENDx goes "0" every time 1-byte data is transmitted (see Figure 8.5).
At initial reset, TENDx is set to "0" (End of transmission).
FER0: Ch.0 framing-error flag (D4) / Serial I/F Ch.0 status register (0x401E2)
FER1: Ch.1 framing-error flag (D4) / Serial I/F Ch.1 status register (0x401E7)
FER2: Ch.2 framing-error flag (D4) / Serial I/F Ch.2 status register (0x401F2)
FER3: Ch.3 framing-error flag (D4) / Serial I/F Ch.3 status register (0x401F7)
Indicates whether a framing error occurred.
Read "1": An error occurred
Read "0": No error occurred
Write "1": Invalid
Write "0": Reset to "0"
The FERx flag is an error flag indicating whether a framing error occurred. When an error has occurred, it is set to "1". A framing error occurs when data with a stop bit = "0" is received in the asynchronous mode.
The FERx flag is reset by writing "0".
At initial reset, as well as when RXENx and TXENx both are set to "0", the FERx flag is set to "0" (no error).
