V DMA BLOCK: IDMA (Intelligent DMA)
The contents of control information (3 words) in each channel are shown in the table below.
Table 3.1 IDMA Control Information
Word | Bit | Name |
|
| Function | |||
1st | D31 | LNKEN | IDMA link enable |
| "1" = Enabled, "0" = Disabled | |||
| LNKCHN[6:0] | IDMA link field |
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| TC[15:0] | Transfer counter (block transfer mode) | ||||||
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| Transfer counter - | |||||
| BLKLEN[7:0] | Block size (block transfer mode) |
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| |||
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| Transfer counter - | |||||
2nd | D31 | DINTEN | "1" = Enabled, "0" = Disabled | |||||
| D30 | DATSIZ | Data size control |
| "1" = | |||
| SRINC[1:0] | Source address control |
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| |||
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| SRINC1 | SRINC0 | Setting contents |
| ||
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| 1 | 1 | Address incremented | |||
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| (In block transfer mode, the transfer address is | |||
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| updated without reset using the initial value.) | |||
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| 1 | 0 | Address incremented | |||
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| (In block transfer mode, the transfer address is | |||
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| updated with the initial value.) | |||
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| 0 | 1 | Address decremented | |||
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| (In block transfer mode, the transfer address is | |||
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| updated without reset using the initial value.) | |||
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| 0 | 0 | Address fixed |
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| SRADR[27:0] | Source address |
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3rd | DMOD[1:0] | Transfer mode (Do not set to "11".) |
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| |||
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| DMOD1 | DMOD0 | Setting contents |
| ||
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| 1 | 0 | Block transfer mode | |||
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| 0 | 1 | Successive transfer mode | |||
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| 0 | 0 | Single transfer mode | |||
| DSINC[1:0] | Destination address control |
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| |||
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| DSINC1 | DSINC0 | Setting contents |
| ||
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| 1 | 1 | Address incremented | |||
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| (In block transfer mode, the transfer address is | |||
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| updated without reset using the initial value.) | |||
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| 1 | 0 | Address incremented | |||
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| (In block transfer mode, the transfer address is | |||
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|
|
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| updated with the initial value.) | |||
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| 0 | 1 | Address decremented | |||
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| (In block transfer mode, the transfer address is | |||
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| updated without reset using the initial value.) | |||
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| 0 | 0 | Address fixed |
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| DSADR[27:0] | Destination address |
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LNKEN: IDMA link enable (D31/1st Word)
If this bit remains set (= "1"), the IDMA channel that is set in the IDMA link field is invoked after the completion of a DMA transfer in this channel. DMA transfers in multiple channels can be performed successively by merely triggering the first channel to be executed. There is no limit to the number of channels linked. Set this link in order of the IDMA channels you want to be executed.
If this bit is "0", IDMA is completed by merely executing a DMA transfer in this channel.
LNKCHN[6:0]: IDMA link field (D[30:24]/1st Word)
If you want IDMA to be linked, set the channel numbers (0 to 127) to be executed next. The data in this field is valid only when LINKEN = "1".
TC[15:0]: Transfer counter (D[23:8]/1st Word)
In block transfer mode, a transfer count can be specified using up to 16 bits. Set this value here. In single transfer and successive transfer modes, a transfer count can be specified using up to 24 bits. Set a
EPSON | S1C33L03 FUNCTION PART |