II CORE BLOCK: CPU AND OPERATING MODE
Notes on Standby Mode
Interrupts
The standby mode can be canceled by an interrupt. Therefore, it is necessary to enable the interrupt to be used for canceling the standby mode before setting the CPU in the standby mode. It is also necessary to set the IE (interrupt enable) and IL (interrupt level) bits in the PSR to a condition that can accept the interrupt. Otherwise, the standby mode cannot be canceled even when an interrupt occurs. Refer to "ITC (Interrupt Controller)", for interrupt settings.
Oscillation circuit
The
The oscillation start time of the
BCU
When the CPU enters the standby mode, the BCU (bus control unit) stops after the current bus cycle has completed. All the chip enable signals are negated.
In basic HALT mode, the BCLK (bus clock) signal is output and DRAM refresh cycles are generated. DMA also operates.
In HALT2 or SLEEP mode, the BCLK signal stops, therefore DRAM refresh cycles cannot be generated and DMA stops.
CPU
Additional
The contents of the CPU registers and input/output port status are retained in the standby mode. Almost all control and data registers of the internal peripheral circuits are also retained, note, however, some registers may be changed at the transition to SLEEP mode. Refer to the section of each peripheral circuit for other precautions.
Test Mode
The C33 Core Block has the ICEMD pin for testing the chip. When this pin is set to High, the IC enters the following state:
•All output pins go into
•Clock inputs are disabled. OSC1, OSC3 and PLL stop operating. OSC2: H, OSC4 H, PLLC: L
•All the
Leave this pin open or connect to VSS for normal operation. The ICEMD pin has a
Debug Mode
The C33 Core Block supports the debug mode.
The debug mode is a CPU function, and realizes single step operation and break functions in the chip itself. Refer to the "S1C33000 Core CPU Manual" for details of the debug mode and the functions.
Area 2 in the memory map can only be accessed in the debug mode.
In the debug mode, the OSC3 clock is used as the CPU operating clock. Therefore, do not stop the
S1C33L03 FUNCTION PART | EPSON |