1 OUTLINE
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| Table 1.3.5 | List of Pins for LCD Controller |
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Pin name | Pin No. | I/O |
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| Function |
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FPDAT[7:4] | O | – | 4 |
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| Data bus for |
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FPDAT[3:0] | O | – | FPDAT[3:0]: 4 |
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GPO[6:3] |
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| GPO[6:3]: |
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FPFRAME | 23 | O | – | Frame pulse output |
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FPLINE | 24 | O | – | Line pulse output |
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FPSHIFT | 25 | O | – | Shift clock output |
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DRDY(MOD) | 22 | O | – | MOD: | LCD backplane bias (for panels other than |
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(FPSHIFT2) |
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| FPSHIFT2: | Second shift clock (for |
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LCDPWR | 26 | O | – | LCD power control output (active high) |
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| Table 1.3.6 | List of Pins for Clock Generator |
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Pin name | Pin No. | I/O |
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| Function |
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OSC1 | 68 | I | – |
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OSC2 | 67 | O | – |
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OSC3 | 129 | I | – |
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OSC4 | 128 | O | – |
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PLLS[1:0] | 112,113 | I | – | PLL |
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| PLLS1 | PLLS0 | fin (fOSC3) | fout (fPSCIN) |
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| 1 | 1 |
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| 0 | 1 |
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| 0 | 0 | PLL is not used | L |
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PLLC | 115 | – | – | Capacitor connecting pin for PLL |
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| Table 1.3.7 List of Other Pins |
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Pin name | Pin No. | I/O |
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| Function |
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/down |
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ICEMD | 125 | I | Pull- |
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| down | When this pin is set to High, all the output pins go into |
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| it possible to disable the S1C33 chip on the board. |
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DSIO | 117 | I/O | Serial I/O pin for debugging |
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| This pin is used to communicate with the debugging tool S5U1C33000H. |
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#X2SPD | 140 | I | – | Clock doubling mode |
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| 1: CPU clock = bus clock ⋅ | 1, 0: CPU clock = bus clock ⋅ 2 |
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#NMI | 130 | I | NMI request input pin |
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#RESET | 69 | I | Initial reset input pin |
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Note: "#" in the pin names indicates that the signal is low active.
S1C33L03 PRODUCT PART | EPSON |