6 BASIC EXTERNAL WIRING DIAGRAM
6 Basic External Wiring Diagram
External
Bus
HSDMA
Serial I/O
A/D input
Timer input/output
Input
I/O
LCD panel
A[23:0] | FPDAT[7:0] FPSHIFT FPFRAME FPLINE DRDY LCDPWR | VDD | |
|
| ||
D[15:0] |
|
| |
#RD |
|
| |
#EMEMRD |
| VDDE | |
#DRD |
| ||
| AVDDE | ||
#GARD |
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#GAAS |
| DSIO | |
#WRL/#WR/#WE | |||
| |||
#WRH/#BSH |
| ICEMD | |
#DWE/#SDWE |
| ||
|
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#HCAS/#SDCAS |
| EA10MD0 | |
#LCAS/#SDRAS |
| ||
|
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#CExx/#RASx/#SDCEx | EA10MD1 | ||
SDA10 |
| ||
|
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SDCKE |
|
| |
HDQM/LDQM |
| #X2SPD | |
#CE10EX |
|
| |
#WAIT |
|
| |
BCLK | S1C33L03 | PLLC | |
#BUSREQ |
| ||
#BUSACK | [The potential of the substrate | PLLS0 | |
#BUSGET | (back of the chip) is VSS.] |
| |
#NMI |
| PLLS1 | |
|
| ||
#DMAREQx |
|
| |
#DMAACKx |
| OSC3 | |
#DMAENDx |
|
| |
SINx |
| OSC4 | |
SOUTx |
|
| |
#SCLKx | OSC1 | |
#SRDYx | ||
| ||
#ADTRG | OSC2 | |
ADx | ||
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EXCLx | #RESET | |
TMx | ||
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T8UFx | VSS | |
Kxx | ||
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Pxx |
|
+
∗1 | R1 | C2 |
| C1 | |
|
|
X'tal2 | CG2 |
or | Rf2 |
CR | CD2 |
| CG1 |
X'tal1 | Rf1 |
| CD1 |
3.3V
X'tal1 | Crystal oscillator | 32.768 kHz, CI(Max.) = 34 kΩ | ∗1: When the PLL is not used, | |
CG1 | Gate capacitor | 10 pF | leave the PLLC pin open. | |
CD1 | Drain capacitor | 10 pF |
| |
Rf1 | Feedback resistor | 10 | MΩ |
|
X'tal2 | Crystal oscillator | 33 | MHz (Max.) |
|
CR | Ceramic oscillator | 33 | MHz (Max.) |
|
CG2 | Gate capacitor | 10 pF |
| |
CD2 | Drain capacitor | 10 pF |
| |
Rf2 | Feedback resistor | 1 MΩ |
| |
R1 | Resistor | 4.7 kΩ |
| |
C1 | Capacitor | 100 pF |
| |
C2 | Capacitor | 5 pF |
| |
Note: The above table is simply an example, and is not guaranteed to work.
EPSON | S1C33L03 PRODUCT PART |