I OUTLINE: BLOCK DIAGRAM

C33 Core Block

The C33 Core Block consists of a functional block C33_CORE including CPU, BCU (Bus Control Unit), ITC (Interrupt Controller), CLG (Clock Generator) and DBG (Debug Unit), an I/O pad block for external interface, and an SBUS (Internal Silicon Integration Bus) for interfacing with on-chip Peripheral Macro Cells. The C33 Core Block employs the S1C33000 32-bit RISC type CPU as the core CPU.

C33 Peripheral Block

The C33 Peripheral Block consists of a prescaler, six channels of 8-bit programmable timer, six channels of 16-bit programmable timer including watchdog timer function, four channels of serial interface, input and I/O ports, and a clock timer.

C33 Analog Block

The C33 Analog Block consists of an A/D converter with eight input channels.

C33 DMA Block

The C33 DMA Block is configured with two types of DMA controllers: HSDMA (High-Speed DMA) that has on-chip registers for controlling DMA command information and IDMA (Intelligent DMA) that uses a memory area for storing DMA command information.

C33 SDRAM Controller Block

The SDRAM Controller Block provides a SDRAM interface that allows direct connection of external SDRAM chips via the BCU.

C33 LCD Controller Block

The LCD Controller Block provides LCD control signals for a 4- or 8-bit color/monochrome LCD panel.

C33 Memory Block

The S1C33L03 contains an 8KB of SRAM as the internal memory.

For details of the blocks, refer to the respective section in this manual.

B-I-2-2

EPSON

S1C33L03 FUNCTION PART