V DMA BLOCK: HSDMA (High-Speed DMA)

A-1

Register name

Address

Bit

Name

Function

 

 

 

 

Setting

Init.

R/W

Remarks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

High-speed

004825A

DF

D3MOD1

Ch.3 transfer mode

D3MOD[1:0]

 

 

 

Mode

0

R/W

 

DMA Ch.3

(HW)

DE

D3MOD0

 

 

1

 

1

 

 

 

Invalid

0

 

 

high-order

 

 

 

 

 

1

 

0

 

 

 

Block

 

 

 

destination

 

 

 

 

 

0

 

1

 

Successive

 

 

 

address set-up

 

 

 

 

 

0

 

0

 

 

 

Single

 

 

 

register

 

DD

D3IN1

D) Ch.3 destination address

D3IN[1:0]

 

 

Inc/dec

0

R/W

 

 

 

DC

D3IN0

control

 

1

 

1

 

Inc.(no init)

0

 

 

Note:

 

 

 

S) Invalid

 

1

 

0

 

 

Inc.(init)

 

 

 

D) Dual address

 

 

 

 

 

0

 

1

 

Dec.(no init)

 

 

 

mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

 

 

Fixed

 

 

 

S) Single

 

 

 

 

 

 

 

 

 

 

 

 

 

DB

D3ADRH11

D) Ch.3 destination

 

 

 

 

 

 

 

 

 

X

R/W

 

address

 

 

 

 

 

 

 

 

 

 

 

 

DA

D3ADRH10

address[27:16]

 

 

 

 

 

 

 

 

 

X

 

 

mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D9

D3ADRH9

S) Invalid

 

 

 

 

 

 

 

 

 

X

 

 

 

 

D8

D3ADRH8

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

D7

D3ADRH7

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

D6

D3ADRH6

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

D5

D3ADRH5

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

D4

D3ADRH4

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

D3

D3ADRH3

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

D2

D3ADRH2

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

D1

D3ADRH1

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

D0

D3ADRH0

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

High-speed

004825C

DF–1

–

reserved

 

 

 

 

 

–

 

 

–

–

Undefined in read.

DMA Ch.3

(HW)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

enable register

 

D0

HS3_EN

Ch.3 enable

1

 

Enable

 

0

 

Disable

0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

High-speed

004825E

DF–1

–

reserved

 

 

 

 

 

–

 

 

–

–

Undefined in read.

DMA Ch.3

(HW)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

trigger flag

 

D0

HS3_TF

Ch.3 trigger flag clear (writing)

1

 

Clear

 

 

0

 

No operation

0

R/W

 

register

 

 

 

Ch.3 trigger flag status (reading)

1

 

Set

 

 

0

 

Cleared

 

 

 

CFK51–CFK50: K5[1:0] pin function selection (D[1:0]) / K5 function select register (0x402C0)

CFK54–CFK53: K5[4:3] pin function selection (D[4:3]) / K5 function select register (0x402C0)

Set the #DMAREQx pin of HSDMA.

Write "1": #DMAREQx input

Write "0": Input port

Read: Valid

CFK50, CFK51, CFK53 and CFK54 are the function select bits for K50 (#DMAREQ0), K51 (#DMAREQ1), K53 (#DMAREQ2) and K54 (#DMAREQ3), respectively. When using the #DMAREQx signal, write "1" to CFK5x to set the K5x port for inputting the signal.

If this bit is set to "0", the pin is set for an input port.

At cold start, CFK5x is set to "0" (input port). At hot start, CFK5x retains the previous status before an initial reset.

CFP16–CFP15: P1[6:5] pin function selection (D[6:5]) / P1 function select register (0x402D4)

Set the #DMAENDx pin of HSDMA.

Write "1": #DMAENDx output

Write "0": I/O port

Read: Valid

When using the #DMAEND0 signal, set the P15 pin for the #DMAEND0 output pin by writing "1" to CFP15. Similarly, when using the #DMAEND1 signal, set the P16 pin for the #DMAEND1 output pin by writing "1" to CFP16. Furthermore, direct these pins for output by writing "1" to the corresponding I/O control register.

If CFP1x is set to "0", the pin is set for an I/O port.

At cold start, CFP1x is set to "0" (I/O port). At hot start, CFP1x retains the previous status before an initial reset.

B-V

HSDMA

S1C33L03 FUNCTION PART

EPSON

B-V-2-27