4 PERIPHERAL CIRCUITS
Register name | Address | Bit | Name | Function |
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| Setting | Init. | R/W | Remarks | ||||
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0048228 | DF | D0ADRL15 | D) Ch.0 destination address[15:0] |
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| X | R/W |
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DMA Ch.0 | (HW) | DE | D0ADRL14 | S) Invalid |
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| X |
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| DD | D0ADRL13 |
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| X |
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destination |
| DC | D0ADRL12 |
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| X |
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address |
| DB | D0ADRL11 |
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| X |
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register |
| DA | D0ADRL10 |
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| X |
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| D9 | D0ADRL9 |
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| X |
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Note: |
| D8 | D0ADRL8 |
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| X |
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D) Dual address |
| D7 | D0ADRL7 |
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| X |
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mode |
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| D6 | D0ADRL6 |
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| X |
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S) Single |
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| D5 | D0ADRL5 |
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| X |
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address |
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| D4 | D0ADRL4 |
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| X |
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mode |
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| D3 | D0ADRL3 |
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| X |
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| D2 | D0ADRL2 |
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| X |
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| D1 | D0ADRL1 |
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| X |
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| D0 | D0ADRL0 |
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| X |
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004822A | DF | D0MOD1 | Ch.0 transfer mode | D0MOD[1:0] |
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| Mode | 0 | R/W |
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DMA Ch.0 | (HW) | DE | D0MOD0 |
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| 1 |
| 1 |
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| Invalid | 0 |
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| 1 |
| 0 |
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| Block |
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destination |
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| 0 |
| 1 |
| Successive |
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address |
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| 0 |
| 0 |
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| Single |
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register |
| DD | D0IN1 | D) Ch.0 destination address | D0IN[1:0] |
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| Inc/dec | 0 | R/W |
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| DC | D0IN0 | control |
| 1 |
| 1 |
| Inc.(no init) | 0 |
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Note: |
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| S) Invalid |
| 1 |
| 0 |
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| Inc.(init) |
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D) Dual address |
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| 0 |
| 1 |
| Dec.(no init) |
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mode |
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| 0 |
| 0 |
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| Fixed |
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S) Single |
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| DB | D0ADRH11 | D) Ch.0 destination |
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| X | R/W |
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address |
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| DA | D0ADRH10 | address[27:16] |
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| X |
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mode |
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| D9 | D0ADRH9 | S) Invalid |
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| X |
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| D8 | D0ADRH8 |
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| X |
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| D7 | D0ADRH7 |
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| X |
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| D6 | D0ADRH6 |
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| X |
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| D5 | D0ADRH5 |
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| X |
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| D4 | D0ADRH4 |
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| X |
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| D3 | D0ADRH3 |
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| X |
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| D2 | D0ADRH2 |
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| X |
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| D1 | D0ADRH1 |
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| X |
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| D0 | D0ADRH0 |
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| X |
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004822C | – | reserved |
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| – |
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| – | – | Undefined in read. | |||
DMA Ch.0 | (HW) |
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enable register |
| D0 | HS0_EN | Ch.0 enable | 1 |
| Enable |
| 0 |
| Disable | 0 | R/W |
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004822E | – | reserved |
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| – |
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| – | – | Undefined in read. | |||
DMA Ch.0 | (HW) |
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trigger flag |
| D0 | HS0_TF | Ch.0 trigger flag clear (writing) | 1 |
| Clear |
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| 0 |
| No operation | 0 | R/W |
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register |
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| Ch.0 trigger flag status (reading) | 1 |
| Set |
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| 0 |
| Cleared |
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EPSON | S1C33L03 PRODUCT PART |