II CORE BLOCK: ITC (Interrupt Controller)
Register name | Address | Bit | Name | Function |
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| Setting | Init. | R/W | Remarks | |||
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Areas | 0048126 | DF | – | reserved |
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| – |
| – | – | 0 when being read. | |
(HW) | DE | A10IR2 | Area 10 internal ROM size | A10IR[2:0] |
| ROM size | 1 | R/W |
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| DD | A10IR1 | selection | 1 |
| 1 | 1 |
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| 2MB | 1 |
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| DC | A10IR0 |
| 1 |
| 1 | 0 |
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| 1MB | 1 |
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| 1 |
| 0 | 1 |
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| 512KB |
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| 1 |
| 0 | 0 |
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| 256KB |
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| 0 |
| 1 | 1 |
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| 128KB |
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| 0 |
| 1 | 0 |
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| 64KB |
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| 0 |
| 0 | 1 |
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| 32KB |
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| 0 |
| 0 | 0 |
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| 16KB |
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| DB | – | reserved |
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| – |
| – | – | 0 when being read. | |
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| DA | A10BW1 | Areas | A10BW[1:0] |
| Wait cycles | 0 | R/W |
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| D9 | A10BW0 | burst ROM | 1 |
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| 1 |
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| 3 | 0 |
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| burst read cycle wait control | 1 |
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| 0 |
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| 2 |
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| 0 |
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| 1 |
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| 1 |
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| 0 |
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| 0 |
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| 0 |
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| D8 | A10DRA | Area 10 burst ROM selection | 1 | Used |
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| 0 | Not used | 0 | R/W |
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| D7 | A9DRA | Area 9 burst ROM selection | 1 | Used |
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| 0 | Not used | 0 | R/W |
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| D6 | A10SZ | Areas | 1 | 8 bits |
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| 0 | 16 bits | 0 | R/W |
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| D5 | A10DF1 | Areas | A10DF[1:0] | Number of cycles | 1 | R/W |
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| D4 | A10DF0 | output disable delay time | 1 |
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| 1 |
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| 3.5 | 1 |
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| 1 |
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| 0 |
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| 2.5 |
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| 0 |
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| 1 |
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| 1.5 |
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| 0 |
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| 0 |
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| 0.5 |
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| D3 | – | reserved |
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| – |
| – | – | 0 when being read. | |
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| D2 | A10WT2 | Areas | A10WT[2:0] |
| Wait cycles | 1 | R/W |
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| D1 | A10WT1 |
| 1 |
| 1 | 1 |
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| 7 | 1 |
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| D0 | A10WT0 |
| 1 |
| 1 | 0 |
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| 6 | 1 |
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| 1 |
| 0 | 1 |
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| 5 |
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| 1 |
| 0 | 0 |
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| 4 |
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| 0 |
| 1 | 1 |
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| 3 |
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| 0 |
| 1 | 0 |
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| 2 |
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| 0 |
| 0 | 1 |
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| 1 |
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| 0 |
| 0 | 0 |
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| 0 |
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The following collectively explains the basic functions of each control register/bit. For details about individual interrupt systems and the contents classified by an interrupt factor, refer to the descriptions of the peripheral circuits in this manual.
Set the priority levels of each interrupt system in the range of 0 to 7.
If this register is set below the IL value of the PSR, no interrupt is generated. The value of this register when initially reset is indeterminate.
Exxx: Interrupt enable register
Enable or disable interrupt generation to the CPU.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
Read: Valid
Interrupts are enabled when the corresponding bits of this register are set to "1" and are disabled when the bits are set to "0".
For the interrupt factors used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable.
When initially reset, this register is set to "0" (interrupt disabled).
EPSON | S1C33L03 FUNCTION PART |