II CORE BLOCK: CLG (Clock Generator)
I/O Pins of Clock Generator
Table 6.1 lists the I/O pins of the clock generator.
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| Table 6.1 I/O Pins of Clock Generator |
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Pin name | I/O |
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OSC3 | I |
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| Crystal/ceramic oscillation or external clock input |
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OSC4 | O |
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| Crystal/ceramic oscillation (open when external clock is used) |
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PLLC | – | Capasitor connecting pin for PLL |
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PLLS[1:0] | I | PLL |
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| PLLS1 | PLLS0 | fin (fOSC3) | fout (fPSCIN) |
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| 1 | 1 |
| ∗ 1 | ||
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| 0 | 1 |
| ∗ 1 | ||
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| 0 | 0 | PLL is not used | L | ∗ 2 | ||
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| ∗ 1: |
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| ∗ 2: When the PLL is not used, the OSC3 clock is used directly. |
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The
This circuit can be a crystal or a ceramic oscillation circuit. Optionally an external clock source can be used. Figure 6.2 shows the structure of the
CG2 | OSC3 |
| OSC3 |
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| VDD |
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| X'tal2 | fOSC3 | VSS | fOSC3 | |
Rf |
| External |
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or |
| clock |
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| Ceramic |
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| Oscillation circuit | N.C. | Oscillation circuit | |
| OSC4 | control signal | control signal | ||
CD2 | OSC4 | ||||
| SLEEP status | SLEEP status | |||
VSS |
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| (1) Crystal/ceramic oscillation circuit |
| (2) External clock input |
Figure 6.2
When using a crystal or a ceramic oscillation for this circuit, connect a crystal (X'tal2) or ceramic (Ceramic) resonator and feedback resistor (Rf) between the OSC3 and OSC4 pins, and two capacitors (CG2, CD2) between the OSC3 pin and VSS and the OSC4 pin and VSS, respectively.
When an external clock is used, leave the OSC4 pin open and input a
The range of oscillation frequencies is 10 MHz to 33 MHz. This frequency range also applies when an external clock is used.
Note: When using the PLL, the oscillation frequency range changes according to the PLL setting. See Table 6.2.
For details on oscillation characteristics and the external clock input characteristics, refer to "Electrical Characteristics".
EPSON | S1C33L03 FUNCTION PART |