II CORE BLOCK: CLG (Clock Generator)

Table 6.6 Operating Status in Standby Mode

Standby mode

 

Operating status

Reactivating factor

HALT mode

Basic mode

•

The CPU clock is stopped. (CPU stop status)

• Reset, NMI

 

 

• BCU clock is supplied. (BCU run status)

• Enabled (not masked) interrupt

 

 

•

DMA clock is not stopped. (DMA run status)

factors

 

 

• Clocks for the peripheral circuits maintain the

 

 

 

 

status before entering HALT mode. (run or

 

 

 

 

stop)

 

 

 

• The high-speed oscillation circuit maintains

 

 

 

 

the status before entering HALT mode.

 

 

 

• The low-speed oscillation circuit maintains

 

 

 

 

the status before entering HALT mode.

 

 

HALT2 mode

•

The CPU clock is stopped. (CPU stop status)

A restart is possible only in the

 

 

• BCU clock is stopped. (BCU stop status)

case of:

 

 

•

DMA clock is stopped. (DMA stop status)

• Reset, NMI

 

 

• Clocks for the peripheral circuits maintain the

• Enabled (not masked) interrupt

 

 

 

status before entering HALT mode. (run or

factors

 

 

 

stop)

Note, however, that an interrupt

 

 

• The high-speed oscillation circuit maintains

from a peripheral circuit can restart

 

 

 

the status before entering HALT mode.

the CPU only when the operating

 

 

• The low-speed oscillation circuit maintains

clock is supplied to the peripheral

 

 

 

the status before entering HALT mode.

circuit.

SLEEP mode

•

The CPU clock is stopped. (CPU stop status)

• Reset, NMI

 

 

• BCU clock is stopped. (BCU stop status)

• Enabled (not masked) input port

 

 

• Clocks for the peripheral circuits are stopped.

interrupt factors

 

 

• The high-speed oscillation circuit is stopped.

• Clock timer interrupt when the

 

 

• The low-speed oscillation circuit maintains

low-speed oscillation circuit is

 

 

 

the status before entering SLEEP mode.

being operated

CLGP7–CLGP0:Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E)

These bits remove the protection against writing to addresses 0x40180 and 0x40190.

Write "0b10010110": Write protection removed

Write other than the above: No operation (write-protected)

Read: Valid

Before writing to address 0x40180 or 0x40190, set CLGP[7:0] to "0b10010110" to remove the protection against writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to "0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to.

At initial reset, CLGP is set to "0b00000000" (write-protected).

B-II-6-8

EPSON

S1C33L03 FUNCTION PART