VII LCD CONTROLLER BLOCK: LCD CONTROLLER
Register name | Address | Bit | Name | Function |
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| Setting | Init. | R/W | Remarks | ||||
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Screen 1 | 039FFF3 | – | reserved |
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| – |
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| – | – | 0 when being read. | ||
vertical size | (B) | D1 | S1VSIZE9 | Screen 1 vertical size |
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| 0 | R/W |
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register 1 |
| D0 | S1VSIZE8 |
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| 0 |
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FIFO control | 039FFF4 | D7 | – | reserved |
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| – |
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| – | – | 0 when being read. | |
register | (B) | D6 | FIFOEO3 | FIFO empty offset |
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| Fix at 8 (0b1000) | 0 | R/W |
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| D5 | FIFOEO2 |
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| 0 |
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| D4 | FIFOEO1 |
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| 0 |
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| D3 | FIFOEO0 |
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| 0 |
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| D2 | LCLKSEL2 | LCDC clock select | LCLKSEL[2:0] |
| LCDC clock | 0 | R/W |
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| D1 | LCLKSEL1 |
| 1 |
| 1 | 1 |
| BCU_CLK/4 | 0 |
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| D0 | LCLKSEL0 |
| 1 |
| 1 | 0 |
| BCU_CLK/3 | 0 |
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| 1 |
| 0 | 1 |
| BCU_CLK/2 |
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| 1 |
| 0 | 0 |
| BCU_CLK |
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| 0 |
| 1 | 1 |
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| reserved |
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| 0 |
| 1 | 0 |
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| Stop |
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| 0 |
| 0 | 1 |
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| Stop |
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| 0 |
| 0 | 0 |
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| Stop |
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039FFF5 | – | reserved |
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| – |
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| – | – | 0 when being read. | |||
address | (B) | D3 | LUTADDR3 |
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| 0 | R/W |
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register |
| D2 | LUTADDR2 |
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| 0 |
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| D1 | LUTADDR1 |
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| 0 |
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| D0 | LUTADDR0 |
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| 0 |
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039FFF7 | D7 | LUTDT3 |
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| 0 | R/W |
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data register | (B) | D6 | LUTDT2 |
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| 0 |
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| D5 | LUTDT1 |
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| 0 |
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| D4 | LUTDT0 |
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| 0 |
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| – | reserved |
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| – |
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| – | – | 0 when being read. | ||
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GPIO | 039FFF8 | – | reserved |
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| – |
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| – | – | 0 when being read. | ||
configuration | (B) | D2 | GPIO2C | GPIO2 configuration | 1 | Output |
| 0 |
| Input | 0 | R/W |
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register |
| D1 | GPIO1C | GPIO1 configuration | 1 | Output |
| 0 |
| Input | 0 | R/W |
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| D0 | GPIO0C | GPIO0 configuration | 1 | Output |
| 0 |
| Input | 0 | R/W |
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GPIO | 039FFF9 | D7 | – | reserved |
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| – |
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| – | – | 0 when being read. | |
status/control | (B) | D6 | GPO6D | GPO6 data | 1 | High |
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| 0 |
| Low | 0 | R/W |
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register |
| D5 | GPO5D | GPO5 data | 1 | High |
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| 0 |
| Low | 0 | R/W |
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| D4 | GPO4D | GPO4 data | 1 | High |
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| 0 |
| Low | 0 | R/W |
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| D3 | GPO3D | GPO3 data | 1 | High |
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| 0 |
| Low | 0 | R/W |
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| D2 | GPIO2D | GPIO2 data | 1 | High |
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| 0 |
| Low | 0 | R/W |
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| D1 | GPIO1D | GPIO1 data | 1 | High |
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| 0 |
| Low | 0 | R/W |
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| D0 | GPIO0D | GPIO0 data | 1 | High |
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| 0 |
| Low | 0 | R/W |
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Scratch pad | 039FFFA | D7 | SP1A7 | Scratch pad |
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| 0 | R/W |
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register | (B) | D6 | SP1A6 |
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| 0 |
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| D5 | SP1A5 |
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| 0 |
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| D4 | SP1A4 |
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| 0 |
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| D3 | SP1A3 |
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| 0 |
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| D2 | SP1A2 |
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| 0 |
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| D1 | SP1A1 |
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| 0 |
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| D0 | SP1A0 |
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| 0 |
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Portrait mode | 039FFFB | D7 | PMODEN | Portrait mode enable | 1 | Portrait |
| 0 |
| Landscape | 0 | R/W |
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register | (B) | D6 | PMODSEL | Portrait mode select | 1 | Alternate |
| 0 |
| Default | 0 | R/W |
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| – | reserved |
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| – |
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| – | – | 0 when being read. | ||
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| D1 | PMODCLK1 | Portrait mode clock select | PMODCLK[1:0] | Division ratio 1 | 0 | R/W |
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| D0 | PMODCLK0 | (LCDC clock division ratio) | 1 |
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| 1 |
| P: 1/8, M: 1/8 | 0 |
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| 1 |
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| 0 |
| P: 1/4, M: 1/4 |
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| Division ratio 1: Default mode | 0 |
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| 1 |
| P: 1/2, M: 1/2 |
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| Division ratio 2: Alternate mode | 0 |
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| 0 |
| P: 1/1, M: 1/1 |
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| P: Pixel clock, M: Memory clock | PMODCLK[1:0] | Division ratio 2 |
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| 1 |
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| P: 1/8, M: 1/4 |
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| 1 |
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| 0 |
| P: 1/4, M: 1/2 |
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| 0 |
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| 1 |
| P: 1/2, M: 1/1 |
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| 0 |
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| 0 |
| P: 1/2, M: 1/1 |
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Line byte | 039FFFC | D7 | PMODLBC7 | Line byte count |
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| 0 | R/W |
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count register | (B) | D6 | PMODLBC6 |
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| 0 |
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for portrait |
| D5 | PMODLBC5 |
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| 0 |
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mode |
| D4 | PMODLBC4 |
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| 0 |
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| D3 | PMODLBC3 |
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| 0 |
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| D2 | PMODLBC2 |
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| 0 |
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| D1 | PMODLBC1 |
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| 0 |
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| D0 | PMODLBC0 |
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| 0 |
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LCDC
S1C33L03 FUNCTION PART | EPSON |