III PERIPHERAL BLOCK: SERIAL INTERFACE
Register name | Address | Bit | Name | Function |
|
|
|
| Setting |
| Init. | R/W | Remarks | |||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||
Serial I/F Ch.3 | 00401F5 | D7 | TXD37 | Serial I/F Ch.3 transmit data |
|
|
| 0x0 to 0xFF(0x7F) | X | R/W |
| |||||
transmit data | (B) | D6 | TXD36 | TXD37(36) = MSB |
|
|
|
|
|
|
|
|
| X |
|
|
register |
| D5 | TXD35 | TXD30 = LSB |
|
|
|
|
|
|
|
|
| X |
|
|
|
| D4 | TXD34 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D3 | TXD33 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D2 | TXD32 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D1 | TXD31 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D0 | TXD30 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| ||
Serial I/F Ch.3 | 00401F6 | D7 | RXD37 | Serial I/F Ch.3 receive data |
|
|
| 0x0 to 0xFF(0x7F) | X | R |
| |||||
receive data | (B) | D6 | RXD36 | RXD37(36) = MSB |
|
|
|
|
|
|
|
|
| X |
|
|
register |
| D5 | RXD35 | RXD30 = LSB |
|
|
|
|
|
|
|
|
| X |
|
|
|
| D4 | RXD34 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D3 | RXD33 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D2 | RXD32 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D1 | RXD31 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D0 | RXD30 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Serial I/F Ch.3 | 00401F7 | – | reserved |
|
|
|
|
|
| – |
| – | – | 0 when being read. | ||
status register | (B) | D5 | TEND3 | Ch.3 | 1 |
| Transmitting |
| 0 | End | 0 | R |
| |||
|
| D4 | FER3 | Ch.3 flaming error flag | 1 |
| Error |
|
|
| 0 | Normal | 0 | R/W | Reset by writing 0. | |
|
| D3 | PER3 | Ch.3 parity error flag | 1 |
| Error |
|
|
| 0 | Normal | 0 | R/W | Reset by writing 0. | |
|
| D2 | OER3 | Ch.3 overrun error flag | 1 |
| Error |
|
|
| 0 | Normal | 0 | R/W | Reset by writing 0. | |
|
| D1 | TDBE3 | Ch.3 transmit data buffer empty | 1 |
| Empty |
|
| 0 | Buffer full | 1 | R |
| ||
|
| D0 | RDBF3 | Ch.3 receive data buffer full | 1 |
| Buffer full |
|
| 0 | Empty | 0 | R |
| ||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Serial I/F Ch.3 | 00401F8 | D7 | TXEN3 | Ch.3 transmit enable | 1 |
| Enabled |
|
| 0 | Disabled | 0 | R/W |
| ||
control register | (B) | D6 | RXEN3 | Ch.3 receive enable | 1 |
| Enabled |
|
| 0 | Disabled | 0 | R/W |
| ||
|
| D5 | EPR3 | Ch.3 parity enable | 1 |
| With parity |
| 0 | No parity | X | R/W | Valid only in | |||
|
| D4 | PMD3 | Ch.3 parity mode selection | 1 |
| Odd |
|
|
| 0 | Even | X | R/W | asynchronous mode. | |
|
| D3 | STPB3 | Ch.3 stop bit selection | 1 |
| 2 bits |
|
|
| 0 | 1 bit | X | R/W |
| |
|
| D2 | SSCK3 | Ch.3 input clock selection | 1 |
| #SCLK3 |
|
| 0 | Internal clock | X | R/W |
| ||
|
| D1 | SMD31 | Ch.3 transfer mode selection | SMD3[1:0] |
| Transfer mode | X | R/W |
| ||||||
|
| D0 | SMD30 |
|
| 1 |
| 1 | X |
|
| |||||
|
|
|
|
|
| 1 |
| 0 |
|
|
| |||||
|
|
|
|
|
| 0 |
| 1 |
| Clock sync. Slave |
|
|
| |||
|
|
|
|
|
| 0 |
| 0 | Clock sync. Master |
|
|
| ||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Serial I/F Ch.3 | 00401F9 | – | reserved |
|
|
|
|
|
| – |
| – | – | 0 when being read. | ||
IrDA register | (B) | D4 | DIVMD3 | Ch.3 async. clock division ratio | 1 |
| 1/8 |
|
|
| 0 | 1/16 | X | R/W |
| |
|
| D3 | IRTL3 | Ch.3 IrDA I/F output logic inversion | 1 |
| Inverted |
|
| 0 | Direct | X | R/W | Valid only in | ||
|
| D2 | IRRL3 | Ch.3 IrDA I/F input logic inversion | 1 |
| Inverted |
|
| 0 | Direct | X | R/W | asynchronous mode. | ||
|
| D1 | IRMD31 | Ch.3 interface mode selection | IRMD3[1:0] |
|
| I/F mode | X | R/W |
| |||||
|
| D0 | IRMD30 |
|
| 1 |
| 1 |
|
| reserved | X |
|
| ||
|
|
|
|
|
| 1 |
| 0 |
|
| IrDA 1.0 |
|
|
| ||
|
|
|
|
|
| 0 |
| 1 |
|
| reserved |
|
|
| ||
|
|
|
|
|
| 0 |
| 0 |
|
| General I/F |
|
|
| ||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
0040269 | D7 | – | reserved |
|
|
|
|
|
| – |
| – | – | 0 when being read. | ||
serial I/F Ch.0 | (B) | D6 | PSIO02 | Serial interface Ch.0 |
|
|
|
| 0 to 7 |
| X | R/W |
| |||
interrupt |
| D5 | PSIO01 | interrupt level |
|
|
|
|
|
|
|
|
| X |
|
|
priority register |
| D4 | PSIO00 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D3 | – | reserved |
|
|
|
|
|
| – |
| – | – | 0 when being read. | |
|
| D2 | P8TM2 |
|
|
|
| 0 to 7 |
| X | R/W |
| ||||
|
| D1 | P8TM1 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D0 | P8TM0 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Serial I/F Ch.1, | 004026A | D7 | – | reserved |
|
|
|
|
|
| – |
| – | – | 0 when being read. | |
A/D interrupt | (B) | D6 | PAD2 | A/D converter interrupt level |
|
|
|
| 0 to 7 |
| X | R/W |
| |||
priority register |
| D5 | PAD1 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D4 | PAD0 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
| D3 | – | reserved |
|
|
|
|
|
| – |
| – | – | 0 when being read. | |
|
| D2 | PSIO12 | Serial interface Ch.1 |
|
|
|
| 0 to 7 |
| X | R/W |
| |||
|
| D1 | PSIO11 | interrupt level |
|
|
|
|
|
|
|
|
| X |
|
|
|
| D0 | PSIO10 |
|
|
|
|
|
|
|
|
|
| X |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Serial I/F | 0040276 | – | reserved |
|
|
|
|
|
| – |
| – | – | 0 when being read. | ||
interrupt | (B) | D5 | ESTX1 | SIF Ch.1 transmit buffer empty | 1 |
| Enabled |
|
| 0 | Disabled | 0 | R/W |
| ||
enable register |
| D4 | ESRX1 | SIF Ch.1 receive buffer full |
|
|
|
|
|
|
|
|
| 0 | R/W |
|
|
| D3 | ESERR1 | SIF Ch.1 receive error |
|
|
|
|
|
|
|
|
| 0 | R/W |
|
|
| D2 | ESTX0 | SIF Ch.0 transmit buffer empty |
|
|
|
|
|
|
|
|
| 0 | R/W |
|
|
| D1 | ESRX0 | SIF Ch.0 receive buffer full |
|
|
|
|
|
|
|
|
| 0 | R/W |
|
|
| D0 | ESERR0 | SIF Ch.0 receive error |
|
|
|
|
|
|
|
|
| 0 | R/W |
|
EPSON | S1C33L03 FUNCTION PART |