III PERIPHERAL BLOCK: SERIAL INTERFACE
ESERR0, ESRX0, ESTX0: Ch.0 interrupt enable (D0,D1,D2) / Serial I/F interrupt enable register (0x40276)
ESERR1, ESRX1, ESTX1: Ch.1 interrupt enable (D3,D4,D5) / Serial I/F interrupt enable register (0x40276)
Enable or disable interrupt generation to the CPU.
Write "1": Interrupt enabled
Write "0": Interrupt disabled
Read: Valid
The ESERRx, ESRXx, and ESTXx bits are interrupt enable bits corresponding to
At initial reset, all these bits are set to "0" (interrupts disabled).
FSERR0, FSRX0, FSTX0: Ch.0 interrupt factor flags (D0,D1,D2) / Serial I/F interrupt factor flag register (0x40286)
FSERR1, FSRX1, FSTX1: Ch.1 interrupt factor flags (D3,D4,D5) / Serial I/F interrupt factor flag register (0x40286)
Indicate the status of
When read
Read "1": An interrupt factor occurred
Read "0": No interrupt factor occurred
When written using the
Write "1": Flag is reset
Write "0": Invalid
When written using the read/write method
Write "1": Flag is set
Write "0": Flag is reset
The FSERRx, FSRXx, and FSTXx flags are interrupt factor flags corresponding to
A
A
A
1.The corresponding interrupt enable register bit is set to "1".
2.No other interrupt request of a higher priority has been generated.
3.The PSR's IE bit is set to "1" (interrupts enabled).
4.The set value of the corresponding interrupt priority register is higher than the CPU interrupt level (IL).
When using the
The interrupt factor flag is set to "1" whenever an interrupt factor occurs, regardless of the settings of the interrupt- enable and interrupt priority registers.
If the next interrupt is to be accepted following the occurrence of an interrupt, it is necessary that the interrupt factor flag be reset, and that the PSR be set up again (by setting the IE bit to "1" after setting the IL to a value lower than the level indicated by the interrupt priority register, or by executing the reti instruction).
The interrupt factor flag can only be reset by writing to it in the software. Note that if the PSR is set up again to accept interrupts generated (or if the reti instruction is executed) without resetting the interrupt factor flag, the same interrupt occurs again. Note also that the value to be written to reset the flag is "1" when the
At initial reset, all of these flags become indeterminate, so be sure to reset them in the software.
SIF
S1C33L03 FUNCTION PART | EPSON |