VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
Enabling/disabling bank interleaved access
A bank cannot be accessed at the same time it is being precharged, so another bank may be accessed during that period, which results in increased access speed. For this purpose, the SDRAM controller supports a feature known as Bank Interleaved Access.
Specify whether or not to use this feature with the SDRBI (D5)/SDRAM advanced control register (0x39FFC9).
SDRBI = "1": Bank interleaved access function is used
SDRBI = "0": Bank interleaved access function is not used (one bank only is accessed at a time)
When SDRBI = "0" |
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| (CAS latency = 2, tRCD = 2) | ||||
BCLK |
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Command | ACTV |
| READ | NOP | PRE | NOP | ACTV | NOP | READ | NOP | PRE | NOP ACTV |
SDCKE | H |
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#SDCEx |
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#SDRAS |
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#SDCAS |
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#SDWE |
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SDBA[1:0] | BA1 |
| BA1 |
| BA1 |
| BA2 |
| BA2 |
| BA2 | BA1 |
SDA[10] | ROW1 |
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| ROW2 |
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| ROW3 |
SDA[12:11, 9:0] | ROW1 |
| COLn |
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| ROW2 |
| CONm |
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| ROW3 |
LDQM/HDQM |
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DQ[15:0] |
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| D(n) |
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| D(m) |
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Bank 1 | Active |
| Read |
| Precharge |
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Bank 2 |
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| Active |
| Read |
| Precharge |
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When SDRBI = "1" |
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| (CAS latency = 2, tRCD = 2) | ||||
BCLK |
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Command | ACTV | ACTV | READ | NOP | READ | NOP | PRE | NOP | ACTV | NOP | READ | NOP |
SDCKE | H |
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#SDCEx |
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#SDRAS |
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#SDCAS |
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#SDWE |
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SDBA[1:0] | BA1 | BA2 | BA1 |
| BA2 |
| BA1 |
| BA1 |
| BA1 |
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SDA[10] | ROW1 | ROW2 |
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| ROW3 |
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SDA[12:11, 9:0] | ROW1 | ROW2 | COLn |
| COLm |
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| ROW3 |
| COLl |
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LDQM/HDQM |
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DQ[15:0] |
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| D(n) |
| D(m) |
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| D(l) |
Bank 1 | Active |
| Read |
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| Precharge |
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Bank 2 |
| Active |
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| Read |
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| tRRD | CAS latency |
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| tRP |
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Figure 2.6 Bank Interleaved Access
When SDRBI is set to "0", the SDRAM controller issues the precharge command every time the bank to be accessed is changed. This reduces current consumption than that of the bank interleaved access, so set SDRBI to "0" if bank is hardly changed through a series of access.
EPSON | S1C33L03 FUNCTION PART |