III PERIPHERAL BLOCK: 16-BIT PROGRAMMABLE TIMERS

A-1

DE16TU0, DE16TC0: Timer 0 IDMA enable (D6, D7) /

Port input 0–3, HSDMA, 16-bit timer 0 IDMA enable register (0x40294) DE16TU1, DE16TC1: Timer 1 IDMA enable (D0, D1) / 16-bit timer 1–4 IDMA enable register (0x40295) DE16TU2, DE16TC2: Timer 2 IDMA enable (D2, D3) / 16-bit timer 1–4 IDMA enable register (0x40295) DE16TU3, DE16TC3: Timer 3 IDMA enable (D4, D5) / 16-bit timer 1–4 IDMA enable register (0x40295) DE16TU4, DE16TC4: Timer 4 IDMA enable (D6, D7) / 16-bit timer 1–4 IDMA enable register (0x40295) DE16TU5, DE16TC5: Timer 5 IDMA enable (D0, D1) /

16-bit timer 5, 8-bit timer, serial I/F Ch.0 IDMA enable register (0x40296)

Enables IDMA transfer by means of an interrupt factor.

When using the set-only method (default)

Write "1": IDMA enabled

Write "0": Not changed

Read: Valid

When using the read/write method

Write "1": IDMA enabled

Write "0": IDMA disabled

Read: Valid

DE16TUx and DE16TCx are IDMA enable bits corresponding to the comparison B and comparison A interrupt factors, respectively. If the bit is set to "1", the IDMA request by the interrupt factor is enabled. If the bit is set to "0", the IDMA request is disabled.

After an initial reset, these bits are set to "0" (IDMA disabled).

Programming Notes

(1)The 16-bit programmable timers operate only when the prescaler is operating.

(2)When setting the input clock or operation mode, make sure the 16-bit programmable timer is turned off.

(3)If a same value is set to the comparison data A and B registers, a hazard may be generated in the output signal. Therefore, do not set the comparison registers as A = B.

There is no problem when the interrupt function only is used.

(4)When using the output clock, set the comparison data registers as A ≥ 0 and B ≥ 1. The minimum settings are A = 0 and B = 1. In this case, the timer output clock cycle is the input clock ⋅ 1/2.

(5)When the comparison data registers are set as A > B in normal mode, no comparison A interrupt is generated.

In this case, the output signal is fixed at the off level.

In fine mode, no comparison A interrupt is generated when the comparison data registers are set as A > 2 ⋅ B + 1.

(6)After an initial reset, the interrupt factor flag becomes indeterminate. To prevent generation of an unwanted interrupt or IDMA request, be sure to reset this flag and register in the software.

(7)To prevent another interrupt from being generated by the same factor after an interrupt has occurred, be sure to reset the interrupt factor flag before setting the PSR again or executing the reti instruction.

(8)Be aware that unnecessary pulse may be generated according to the control of the clock output and port configuration when a 16-bit programmable timer is used to output the TMx clock.

For example, when TMx is set as inverted output (OUTINVx = "1"), the output waveform falls with the comparison B signal and it rises with the comparison A signal. Furthermore, the output pin is fixed at high level when PTMx is set to "0" to stop the clock output. When switching the output pin to the I/O port pin and then setting the port to low after the TMx signal falls with the comparison A signal, a high level pulse will be generated if "0" is written to PTMx before setting the port to low. It can be prevented by writing "0" to PTMx after setting the port to low.

B-III

16TM

S1C33L03 FUNCTION PART

EPSON

B-III-4-25