II CORE BLOCK: ITC (Interrupt Controller)
DENONLY: IDMA enable register set method selection
(D2) / Flag set/reset method select register (0x4029F)
Select the method for setting the IDMA enable registers.
Write "1":
Write "0": Read/write method
Read: Valid
With the
The IDMA enable bits for which "0" has been written can neither be set nor reset. Therefore, this method ensures that only a specific IDMA enable bit is set. However, when using
The read/write method is selected by writing "0" to DENONLY. When this method is selected, IDMA enable bits can be read and written as for other registers. Therefore, the IDMA enable bit is reset by writing "0" and set by writing "1". In this case all IDMA enable bits for which "0" has been written are reset. Even in a
After an initial reset, DENONLY is set to "1"
SIO2ES0: SIO Ch.2 receive error/FP0 interrupt factor switching
(D0) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": SIO Ch.2 receive error
Write "0": FP0 input
Read: Valid
Set to "1" to use the SIO Ch.2 receive error interrupt.
Set to "0" to use the FP0 input interrupt.
At
SIO2RS0: SIO Ch.2
Switches the interrupt factor.
Write "1": SIO Ch.2
Write "0": FP1 input
Read: Valid
Set to "1" to use the SIO Ch.2
Set to "0" to use the FP1 input interrupt.
At
SIO3ES0: SIO Ch.3 receive error/FP2 interrupt factor switching
(D2) / Interrupt factor FP function switching register (0x402C5)
Switches the interrupt factor.
Write "1": SIO Ch.3 receive error
Write "0": FP2 input
Read: Valid
Set to "1" to use the SIO Ch.3 receive error interrupt.
Set to "0" to use the FP2 input interrupt.
At
ITC
S1C33L03 FUNCTION PART | EPSON |