APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
DRAM: 60ns, CPU: 33MHz, random read/write cycle
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| tRC |
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| RAS cycle |
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| CAS cycle | RAS precharge | ||||||||||
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BCLK |
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| 2 |
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| 2 |
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A[11:0] |
| ROW #1 |
| COL #1 |
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| ROW #2 |
tRAD
tRAH tASC
tASR tRAS tRP
#RAS
tRCD tCAS
#CAS
#RD
tRAC
tOAC
tAA
tCAC |
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| tOFF |
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RD data
D[15:0](RD)
tWP
#WE
tDS tDH
D[15:0](WR) | WR data |
DRAM: 60ns, CPU: 33MHz,
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| tPC |
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| RAS cycle | CAS cycle | CAS cycle | RAS precharge |
| 2 | 2 | 2 | 2 |
BCLK |
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A[11:0] | ROW #1 | COL #1 | COL #2 |
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| tRAS |
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#RAS |
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| tCP |
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#CAS |
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#RD |
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| tACP |
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D[15:0](RD) |
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| RD data |
| RD data |
#WE |
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D[15:0](WR) |
| WR data | WR data |
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DRAM: 60ns, CPU: 33MHz,
RPC delay |
| Fixed | Refresh RAS pulse width |
| RAS precharge | |||||||||
| 1 |
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| 1 |
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| 3 |
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| 2 |
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BCLK
tRAS
#RAS
tRPC tCSR tCHR
#CAS
EPSON | S1C33L03 PRODUCT PART |