
VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE
The SDRAM controller supports three
In HALT2 and SLEEP modes, the SDRAM’s
1.Set SDRSRF (D5/0x39FFC1) to "1" in order to enable the SDRAM’s
2.Check to see that SDRSRM (D6/0x39FFCA) = "0" (i.e., SDRAM is being
3.Execute the HALT or SLP instruction.
Because the OSC3 clock is required for the SDRAM controller to be able to operate, the SDRAM must also be placed in
Note: Because the SDRAM is taken out of
Bus Release Procedure
When the CPU releases the external bus, all of the SDRAM signal input/output pins, except for BCLK output when SDRCLK = "1", are placed in the
The following illustrates a procedure where control of the SDRAM is switched.
BCLK
INTX (external device)
Synchronization
#BUSREQ
#BUSACK
Synchronization
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| The external | bus |
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| S1C33 |
| terminates | master controls |
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| S1C33 controls | ||||||||||||
D[15:0] |
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| the current bus cycle. 1 cycle 1 cycle | bus cycles. |
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A[23:0], #RD, #WR |
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SDRAM status |
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| Self refresh |
| CMD |
| Self refresh |
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CKE (external device) |
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SDCKE (S1C33) |
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SDRAM control (S1C33) | CMD |
| Self refresh |
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| Self refresh | |||||||||||||
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SDRAM control (external device) |
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| Self refresh |
| CMD |
| Self refresh |
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Figure 2.17 Bus Release Procedure
SDRAM
S1C33L03 FUNCTION PART | EPSON |