VII LCD CONTROLLER BLOCK: LCD CONTROLLER

Register name

Address

Bit

Name

Function

 

Setting

 

Init.

R/W

Remarks

 

 

 

 

 

 

 

 

 

 

 

 

 

LCDC

039FFFD

D7

VRAMAR

VRAM area select

1

Area 8

0

 

Area 7

0

R/W

 

system control

(B)

D6

VRAMWT2

VRAM wait control

 

0–7

 

0

R/W

 

register

 

D5

VRAMWT1

(number of wait cycles for SRAM)

 

 

 

 

 

0

 

 

 

 

D4

VRAMWT0

 

 

 

 

 

 

0

 

 

 

 

D3

EDMAEN

External DMA enable

1

Enabled

0

 

Disabled

0

R/W

 

 

 

D2

BREQEN

External bus-request enable

1

Enabled

0

 

Disabled

0

R/W

 

 

 

D1

LCDCST

A0/BSL select

1

BSL

0

 

A0

0

R/W

 

 

 

D0

LCDCEC

Big/little endian select

1

Big endian

0

 

Little endian

0

R/W

 

Note: Addresses 0x39FFFE and 0x39FFFF are assigned for the purpose of inspecting the LCD controller. Writing data to these addresses may damage the LCD controller and the LCD panel to which the LCD controller is connected. Therefore, make sure data is never written to that location.

PCODE[5:0]: Product code (D[7:2]) / Revision code register (0x39FFE0)

The LCD controller’s product code (0b000010) is written here. These bits are read-only, and writing to them has no effect.

RCODE[1:0]: Revision code (D[1:0]) / Revision code register (0x39FFE0)

The LCD controller’s revision code (0b00) is written here. These bits are read-only, and writing to them has no effect.

LDCOLOR: Color/monochrome select (D5) / LCDC mode register 0 (0x39FFE1)

Selects the type of connected LCD panel (color or monochrome).

Write "1":

Color panel

Write "0":

Monochrome panel

Read:

Valid

Setting LDCOLOR to "1" selects a color panel drive method, and setting it to "0" selects a monochrome panel drive method.

At initial reset, LDCOLOR is set to "0" (monochrome panel).

FPSMASK: Mask FPSHIFT signal (D2) / LCDC mode register 0 (0x39FFE1)

Selects the FPSHIFT mask (effective only for color LCD panels).

Write "1": Masked

Write "0": Output

Read: Valid

When FPSMASK is set to "1", the FPSHIFT signal is masked and is not output during the non-display period. When FPSMASK is set to "0", the FPSHIFT signal is output even during the non-display period. This setting is effective only for color LCD panels (LDCOLOR = "1"). When a monochrome LCD panel is used, the FPSHIFT signal is not masked regardless of the setting of this bit.

At initial reset, FPSMASK is set to "0" (output).

LDDW[1:0]: LCD data width/format (D[1:0]) / LCDC mode register 0 (0x39FFE1)

Selects the LCD panel’s data width and format. The contents of selection, including that of LDCOLOR, are listed in Table 2.22.

Table 2.22 Selection of LCD Panels

LDCOLOR

LDDW1

LDDW0

LCD panel

0

0

0

Mono Single 4-bit passive LCD

 

 

1

Mono Single 8-bit passive LCD

 

1

0

Reserved

 

 

1

Reserved

1

0

0

Color Single 4-bit passive LCD

 

 

1

Color Single 8-bit passive LCD format 1

 

1

0

Reserved

 

 

1

Color Single 8-bit passive LCD format 2

At initial reset, LDDW is set to "0b00" (4-bit panel).

B-VII-2-34

EPSON

S1C33L03 FUNCTION PART