IICORE BLOCK: CLG (Clock Generator)
(8)If the IC enters the debug mode through the connected S5U1C33000H (In-Circuit Debugger for S1C33 Family) when the OSC3 clock is divided by 2, 4, or 8 using the CLKDT[1:0] (D[7:6])/Power control register (0x40180) to generate the CPU clock (CPU_CLK), the division ratio is automatically changed to 1/1. This may cause the CPU_CLK frequency to exceed the range assumed. Also it affects the BCU_CLK and BCLK output clocks as they are generated from CPU_CLK. If the BCU_CLK and BCLK output clock frequencies exceed the access time condition or operating range of the devices driven with these clocks, debugging functions such as memory dump as well as program execution may not operate correctly. Therefore, prescribe remedies for malfunctions when debugging, for example, changing the number of wait cycles and other parameters in the BCU registers using the debugger, so that the program can be executed and debugged without problems even when the division ratio changes to 1/1.
(9)When the base clock (CPU operating clock) is generated by dividing the source clock output from OSC3 or PLL by a value (2, 4, or 8) specified using CLKDT[1:0] (D[7:6])/Power control register (0x40180), the peripheral circuit clocks must be set lower than the base clock frequency using the prescaler. If the peripheral circuit clock frequency is equal to or higher than the base clock frequency, the peripheral circuit does not operate normally.
B-II-6-10 | EPSON | S1C33L03 FUNCTION PART |