VI SDRAM CONTROLLER BLOCK: SDRAM INTERFACE

A-1

Refresh Mode

The SDRAM controller supports two SDRAM refresh modes: auto refresh and self-refresh.

Auto refresh

The SDRAM controller incorporates a 12-bit auto refresh counter. This counter continues counting on OSC3 clock edges, and when a specified count is reached, commands are sent to the SDRAM that precharges and auto-refreshes all banks. The counter is reset at that time, and starts counting for the next refresh period. The counter is also reset by self-refresh.

The auto-refresh period is determined by the OSC3 clock frequency and the count value set in the SDRARFC [11:0] (D[B:0])/Auto refresh count register (0x39FFC6). For SDRARFC, set the appropriate value meeting the specifications of your SDRAM. The count value is obtained by the equation below.

SDRARFC ≤

RFP

⋅ tRP - tRCD - 3

–––––––– ⋅ fOSC3 - BL - CL - 2

 

ROWS

 

RFP:

Maximum refresh period [s]

 

ROWS: Row address size

 

fOSC3:

OSC3 clock frequency [Hz]

 

BL:

Burst length [word]

 

CL:

CAS latency [Number of SD_CLK cycles]

tRP:

PRECHARGE command period [Number of SD_CLK cycles]

tRCD:

ACTIVE to READ or WRITE delay time [Number of SD_CLK cycles]

If RFP = 64 ms, ROWS = 4,096, fOSC3 = 20 MHz, BL = 8, CL = 3, tRP = 4, and tRCD = 4, for example, the value to set is calculated as follows:

0.064

SDRARFC ≤ –––––––– ⋅ 20,000,000 - 8 - 3 - 2 ⋅ 4 - 4 - 3 = 286 4,096

Therefore, set any value equal to or less than 286 (0x11E) for SDRARFC.

BCLK

Command

NOP PALL NOP

REF

NOP

REF NOP

SDCKE

H

 

 

 

#SDCEx

 

 

 

 

#SDRAS

 

 

 

 

#SDCAS

 

 

 

 

#SDWE

 

 

 

 

SDBA[1:0]

 

 

 

 

SDA[10]

 

 

 

 

SDA[12:11, 9:0]

 

 

 

 

LDQM/HDQM

L

 

 

 

DQ[15:0]

 

 

 

 

 

tRP

 

tRC

 

 

Figure 2.15

Auto Refresh

 

B-VI

SDRAM

S1C33L03 FUNCTION PART

EPSON

B-VI-2-17